Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-10-29
2002-11-12
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S200000, C365S051000
Reexamination Certificate
active
06480415
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology effective for application to a method of setting redundancy relieving information and trimming information such as a voltage employed in an electrically programmable erasable non-volatile memory, and to a technology effective for use in a flash memory, for example.
In a flash memory, nonvolatile storage or memory elements comprising MOSFETs formed in a two-layer structure having control and floating gates are used for memory cells. The amount of an electrical charge stored in the floating gate is changed to vary the threshold voltage of each MOSFET, thereby storing data in each memory cell.
This type of flash memory is generally provided with an internal power circuit having a booster circuit like a charge pump circuit for generating high voltages necessary for write/erase operations for each memory cell. However, the booster circuit causes predetermined variations even in the generated voltages due to variations in elements constituting the booster circuit. Even as to the MOSFETs constituting the storage elements of the flash memory, parameters such as the thickness or the like of a gate oxide film, the size of each portion of an element, the concentration of an impurity in a drain region, etc. vary due to the difference in process or the like, and correspondingly, a write characteristic and an erase characteristic vary in a predetermined range.
When the voltages generated by the booster circuit and the write and erase characteristics of each storage element vary as described above, the accurate operation of the memory is not assured. Therefore, there is known a technology wherein a trimming circuit is provided to make fine adjustments to each generated time and a write time at a stage subsequent to the fabrication of a chip. A general semiconductor memory including a flash memory is provided with a so-called redundant circuit for replacing a defective bit included in a memory array with its corresponding spare memory cell to improve the yield thereof.
It was conventionally common practice to adopt a system wherein the level setting of the trimming circuit and the setting of substitutional information by the redundant circuit were carried out by using a fuse (hereinafter called “polysilicon fuse”) formed of a polysilicon layer. However, the system using the polysilicon fuse needs a device for breaking or cutting off the polysilicon fuse by laser or the like. Since the subsequent change is unfeasible once it cuts off, the greatest possible care is required upon its cutting-off. A problem also arises in that trimming cannot be performed after the assembly of chips into packages. Therefore, there has also been proposed the invention related to a trimming circuit or a redundant circuit wherein elements identical in structure to nonvolatile storage or memory elements constituting a memory array, which are used in place of the polysilicon fuse, have been used in place of the polysilicon fuse.
SUMMARY OF THE INVENTION
However, the system using the nonvolatile memory elements in place of the polysilicon fuse is accompanied by the problem that since a memory element for a fuse is normally provided independently of a memory array, a dedicated circuit for effecting writing, verify, etc. on the memory element is needed to make circuit's overhead greater, thereby increasing a chip size.
Therefore, the invention has also been proposed wherein a switching element is used in place of the polysilicon fuse, a trimming register for holding trimming information for controlling the switching element is provided and a relieving register for storing substitutional information therein is provided, and the trimming information and substitutional information are stored in a predetermined area lying within a memory array, whereby the information are read from the memory array upon resetting and set to the trimming register and relieving register (Unexamined Patent Publication No. Hei 11(1999) -297086).
However, the prior invention does not make it appear that in which area of the memory array the registers for the trimming information and relief should be stored. When one attempts to store the registers in a normal use area, a problem arises in that storage capacity available for a user is reduced. Further, there is a possibility that the user will accidentally rewrite data written into the trimming information storage area. A problem arises in that when the trimming information is rewritten or updated, the normal operation of a memory is not assured. Further, the registers for the trimming information and relief are provided in a controller, and the information is transferred to each register according to a normal read operation.
An object of the present invention is to make it possible to effect writing, verify, etc. on memory elements for storing trimming information and substitutional information or the like without the provision of a dedicated circuit in an electrically programmable erasable nonvolatile memory device like a flash memory.
Another object of the present invention is to make it possible to avoid a reduction in storage capacity available for a user and misrewriting of data by the user.
The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
Substitutional information for a redundant circuit and adjustment information for a voltage trimming circuit are stored in some of a memory array, and these information are transferred to a latch circuit or a register upon power-up or the like.
Described more specifically, there is provided a nonvolatile semiconductor memory device comprising a memory array comprising a plurality of memory cells wherein which predetermined voltages are applied to selected memory cells to change threshold voltages thereof, thereby storing data therein according to the difference between the threshold voltages. In the nonvolatile semiconductor memory device, some in the memory array are used as spare memory cells, and at least one latch circuit connected to each bit line of the memory array through a transmission switch is provided. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is capable of being transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.
According to the above means, since the substitutional information for the redundant circuit is originally stored in the part of the memory array, it is not necessary to use the polysilicon fuse. It is therefore possible to flexibly set substitutional information and trimming information for each memory cell and effect writing, verify, etc. on each memory or storage element for storing the substitutional information or the like therein without using a dedicated device or providing a dedicated circuit.
Preferably, the memory array includes a set value storage area whose access is restricted in a normal operating state and which is configured writably in a predetermined operation mode, and the substitutional information is capable of being stored in the set value storage area. Thus, the storage capacity available for each user is not reduced. It is also possible to avoid misrewriting of the substitutional information or the like by the user.
Further, the substitutional information stored in the memory array is transferred to and held in the latch circuit through the transmission switch upon power-up. It is thus possible to bring the substitutional information into a state of being held in the latch circuit when the normal operation is allowed.
The latch circuit has a positive-phase and a negative-phase input terminals. The pair of input terminals are connected to any two bit lines of the memory array, and the latch circuit captur
Fujita Akihiro
Kasai Hideo
Makuta Kiichi
Toukairin Atsushi
Wada Masashii
Hoang Huan
Miles & Stockbridge P.C.
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