Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2000-06-22

2002-06-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240

Reexamination Certificate

active

06400601

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having electrically rewritable nonvolatile memory cells, and particularly relates to a multi-valued nonvolatile semiconductor memory device which is capable of storing information corresponding to a plurality of bits per a memory cells.
2. Background Art
EPROMs (Erasable Programmable Read Only Memory) or EEPROMs (Electrically Erasable PROM) have been used as nonvolatile semiconductor memory devices capable of being electrically written into memory cells in the past. However, the recent mainstream tends toward flash memories because of the capability of collective erasure of a erasure block defined as block units in a memory cell array. In a flash memory device, a memory cell comprises a source, a drain, and a floating gate, and a control gate laminated on each other through insulating films. Writing and erasing operations are executed by injection and extraction of electrons for the floating gate using the hot electron effect or the tunneling effect and the writing operation can also be executed utilizing a phenomenon that the threshold value of the memory cell changes with or without electron injection.
Now, there are a few types of memory cells in a flash memory device because of the thickness variation or the inclusion of minute defects in oxide films due to dispersion of manufacturing process. One type of the memory cell is that necessary to write repeatedly because writing is difficult, and another one is, in contrast to the above type, that necessary to complete writing in a short time so as to prevent overwriting. In other words, when writing is executed to all memory cells by an identical condition, the threshold values for those memory cells become diverse so that margins for the operating voltage or the access time become not adjustable.
In order to cope with the above circumstance, the writing operation to the memory cells in the flash memory devices are executed not by one time but by a plurality of times while adjusting writing pulse widths or writing voltages, and always determining a degree of writing until the desired level of the threshold value is attained. This is because, if too many electrons are injected in the floating gate, then, except by executing an erasing operation, it is difficult to restore the gate and that it is possible to erase the flash memory cell only when a collective erasure of a total memory cells or a block unit of the memory cells is carried out, in contrast to the EEPROM, in which the memory cells can be erased individually. The above-mentioned repetitive writing operations allows overcoming the diverse threshold values of the memory cells and it is necessary to recognize the diverse distribution of the threshold values. In fact, the threshold values of all memory cells in a memory cell array are distributed as shown in
FIG. 14
, described later.
In order to reduce the chip size while increasing the memory volume of the memory cells, the memory cells are now changing to store multi-valued data are more than the binary data. For that purpose, the memory cells that can store the multi-valued data is realized by setting the multilevel threshold values or threshold voltages (multilevel cells) in accordance with the data by controlling the amount of electron injected into the floating gate. When each memory cell is made into a multilevel cell, for example, a four valued cell, each memory can store the data corresponding to two bits. When four valued cells are used, the number of memory cells for a flash memory, which originally includes 512 million binary cells can be reduced to 256 million binary cells, which results in reducing the chip area for the memory cells.
Japanese Unexamined Patent Application, First Publication No. Hei 8-315586 discloses a flash memory, the schematic structure of which is shown in FIG.
12
. In the flash memory
100
shown in
FIG. 12
, a plurality of memory cells
101
are arranged in a matrix form. A plurality of word lines extending in the row direction of the cell matrix are connected with a plurality of control gates corresponding to respective word lines. A plurality of bit lines extending in the column direction of the cell matrix are connected to drains of a plurality of memory cells corresponding to respective word lines. The sources of respective memory cells are connected with a common source line (not shown). The row decoder
102
selects one of word lines according to an address signal externally input from the flash memory through an I/O buffer
103
. The I/O buffer
103
is a circuit which forms an interface between the flash memory
100
and the outside.
A combination sense circuit and writing data latch
104
comprises sense amplifiers (not shown) and writing amplifiers (not shown) so as to correspond to each bit line, and one end of the writing data latch
104
is connected to the bit line of the memory cell array
101
, and the other end is connected to the I/O buffer
103
through a column gate
105
. A column decoder
106
controls a column switch constituting the column gate
105
according to the above-mentioned address signal for selecting a bit line designated by the address signal and corresponding to the combination sense circuit and writing data latch
104
. A boosting circuit
107
generates various voltages (for example, high voltages necessary for writing and erasing the memory cell array
101
) for supplying these voltages to the flash memory
100
. A control circuit
108
sends various control signals to various portions of the flash memory
100
for controlling respective portions and making them execute writing and erasing operations.
FIG. 13
shows a detailed structure of a combination sense circuit and writing data latch
104
provided corresponding to one bit line among the sense circuits and writing data latches
104
shown in FIG.
12
. In this conventional example, the flash memory is assumed to be constituted by memory cells which store two bits data (four level data). In this conventional example, when 2-bit data is written in the memory cell, the threshold value corresponding to the data “11” is the lowest, and the threshold values increases in the order of “10”, “01”, and “00”. It is assumed that 2-bit data from “11” to “00” (in
FIG. 14
, MSB is the higher rank bit, and LSB is the lower rank bit) are in the states from the “state 1” to the “state 4”, and that differences of the threshold values separating adjacent threshold values are VREF
1
to VREF
3
. Here, “the state 1” is the state after erasure.
In
FIG. 13
, both reference symbols MSEN and LSEN denote sense amplifiers and both amplifiers are provided with respective latches
110
and
111
constituted by two inverters connected like a loop. The latch
110
stores the higher rank bit and the latch
111
stores the lower rank bit among two bits data.
FIG. 15
is a diagram for explaining the writing operation executed by the circuit shown in FIG.
13
.
FIG. 15
shows a time serial change of data stored in respective latches
110
and
111
for each of the 2-bit data for writing in the memory cells.
Here, the conventional writing operation into the memory cell will be described with reference to
FIGS. 13
to
18
. The details of the circuit shown in
FIG. 13
will not be described, but the operation as a whole will be explained. At first, the threshold value of the memory cell is changed to the value corresponding to the “state 1”. Since the writing data are divided into respective two bits (each “write data” in
FIG. 15
) in the course of delivering the writing data into the column gate
105
externally from the flash memory
100
(
FIG. 12
) through the I/O buffer
103
, the latches
110
and
111
(
FIG. 13
) uptake writing data respectively through the data lines IO and IOB.
As shown below, the writing operation is performed by three stages, and the final writing state is attained by the writing operations executing respective stages shown in FIG.
16
→FIG.
17
→FIG.

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