Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2000-05-08

2001-02-27

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210

Reexamination Certificate

active

06195288

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which holds data stored in a memory cell even if power is turned OFF and more particularly to the nonvolatile semiconductor memory device such as a flash EEPROM.
2. Description of the Related Art
A nonvolatile semiconductor memory device in an example shown in
FIG. 3
includes: memory cells
1
m
(m=1, 2, . . . , M); selecting cells
2
1m
and
2
2m
; a word line
3
; first and second column lines
4
1
and
4
2
; a word line drive circuit
5
; column selecting circuits
6
1
and
6
2
; a reading-out circuit
7
; an inverter
8
; a read-out drive section
9
m
; a reference section
10
; a sense-amplifier
11
m
; and a data bus
12
. Note here that this example is a circuit related to reading out data and a circuit related to data write-in and erasure is not shown.
The memory cell
1
m
includes a MOS transistor which has a usual gate (control gate) and also a floating gate electrically insulated from a surrounding in such a configuration that each control gate is connected through the word line
3
and also, through the word line
3
, connected to an output terminal of the word line drive circuit
5
. In each memory cell
1
m
, when a sufficiently higher voltage (10-20V) than that applied to a drain is applied to the control gate, electrons are stored from the drain into the floating gate (write-in operation) and, when polarity of the voltage applied to the control gate is changed, those electrons stored in the floating gate are moved to the drain (erasure operation). Therefore, in a case where no electrons are stored in the floating gate of each memory cell
1
m
, when a command for reading out data is supplied from outside to permit the word-line drive circuit
5
to apply an “H” level signal to the word line
3
, the “H” level signal is applied to the control gate, thus turning ON the memory cell
1
m
. In a case where electrons are stored in the floating gate, on an other hand, even when the “H” level signal is applied from the word-line drive circuit
5
to the word line
3
to apply the “H” level signal to the control gate, a negative charge of the electrons stored in the floating gate inhibits a channel from being induced, so that the memory cell
1
m
is not turned ON and stays in an OFF-state, thus raising a threshold voltage VT. These ON-states and OFF-states correspond to one-bit states of “0” and “1” respectively.
The selecting cells
2
1m
each consist of a MOS transistor and are connected to one another at their gate through the first column line
4
1
and also, therethrough, to an output terminal of the column selecting circuit
6
1
. The column selecting circuit
6
1
, when the first column line
4
1
is selected as a result of a first-stage decoding of addresses supplied from outside, applies an “H” level signal to that first column line
4
1
. With this, the selecting cell
2
1m
is supplied with the “H” level signal at its gate and so turned ON, to form a path through which data is read out from the memory cell
1
m
.
The selecting cells
2
2m
each consist of a MOS transistor and are connected at their gate to one another through the second column line
4
2
and also, therethrough, to an output terminal of the column selecting circuit
6
2
. The column selecting circuit
6
2
, when that second column line
4
2
is selected as a result of a second-stage decoding of addresses supplied from the outside, applies an “H” level signal to that second column line
4
2
. With this, the selecting cell
2
2m
is supplied with the “H” level signal and so turned ON, to form a path through which data is read out from the memory cell
1
m
.
The reading-out circuit
7
, when supplied with a data-read-out command from the outside, supplies an “H” level signal which indicates a start of a data read-out operation, to the inverter
8
, the read-out driving circuit section
9
m
, and the reference section
10
. The inverter
8
inverts the “H” level signal supplied from the reading-out circuit
7
into an “L” level signal and then supplies it to the read-out driving section
9
, and the reference section
10
.
The read-out driving section
9
m
roughly includes a driving transistor
13
m
, a path forming transistor
14
m
, a path cutting-off transistor
15
m
, and a NOR gate
16
m
.
The driving transistor
13
m
consists of a MOS transistor and is turned ON by an “H” level signal supplied from the reading-out circuit
7
in order to apply a voltage V, which corresponds to an ON-state or OFF-state of the memory cell
1
m
, to a first input terminal of the sense-amplifier
11
m
. The path forming transistor
14
m
consists of a MOS transistor and is turned ON by an “H” level signal supplied from the NOR gate
16
m
. in order to form a path for reading out data from the memory cell
1
m
. The path cutting-off transistor
15
, consists of a MOS transistor and is turned ON by an “H” level signal supplied from the inverter
8
in order to cut off a path for reading out data from the memory cell
1
m
. The NOR gate
16
m
, which has its first input terminal supplied with an output signal of the inverter
8
and its second input terminal connected with a source of the path forming transistor
14
m
, outputs an “H” level signal to turn ON the path forming transistor
14
. when both the output signal of the inverter
8
and the source voltage of the path forming transistor
14
m
are of an “L” level.
The reference section
10
roughly includes a reference cell
21
, selecting cells
22
1
and
22
2
, a word-line driving circuit
23
, column selecting circuits
24
1
and
24
2
, a driving transistor
25
, a path forming transistor
26
, a path cutting-off transistor
27
, and a NOR gate
28
.
The reference cell
21
consists of a MOS transistor having a same construction and characteristics as the memory cell
1
m
and is set beforehand in such a state that no electrons are stored in its floating gate, an ON-state. The selecting cell
22
1
, the selecting cell
22
2
, the word-line driving circuit
23
, the column selecting circuit
24
1
, the column selecting circuit
24
2
, the path forming transistor
26
, the path cutting-out transistor
27
, and the NOR gate
28
have a same construction and characteristics as the selecting cell
21
m
, the selecting cell
22
m
, the word-line driving circuit
5
, the column selecting circuit
6
1
, the column selecting circuit
6
2
, the path forming transistor
14
m
, the path cutting-off transistor
14
m
, the path cutting-out transistor
15
m
, and the NOR gate
16
m
. respectively. This is so set that the sense-amplifier
11
m
, including a differential amplifier, may have its first and second input terminals respectively connected with two loads equal as much as possible.
Since the read-out driving section
9
m
is provided one for each memory cell
1
m
and, on the other hand, the reference section
10
is provided one for M number of the sense-amplifiers
11
m
, the driving transistor
25
generally has two to three times the size of the driving transistor
13
m
in order to acquire a current driving capability. The driving transistor
25
, when turned ON by an “H” level signal supplied from the reading-out circuit
7
, applies a voltage V
R
which corresponds to the ON-state of the reference cell
21
, to the second input terminal of the sense-amplifier
11
m
.
The sense-amplifier
11
m
, as mentioned above, includes a differential amplifier, so that it detects and amplifies a difference between a voltage supplied from the read-out driving section
9
m
and a voltage V
R
supplied from the reference section
10
and then outputs data via the data bus to the outside.
Steady characteristics of such prior-art nonvolatile semiconductor memory device are represented by a curve a for the voltage vs. current characteristic of the driving transistor
13
m
and a curve b for the voltage vs. current characteristics of the driving transistor
25
m
as shown in FIG.
4
. That is, the driving transistors
13
m
and
25

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