Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2000-02-23

2001-10-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185030, C365S185170

Reexamination Certificate

active

06301153

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to an EEPROM (Electrically Erasable PROM).
In recent years, as one type of the EEPROMs, a NAND type flash EEPROM has been proposed.
The above EEPROM includes NAND cell lines each having a plurality of serially connected memory cells and two select transistors connected to both ends of the NAND cell line. When the NAND cell line and the select transistors are considered as one unit, a plurality of units are connected to one bit line. The memory cell has a stack gate structure including a floating gate electrode and a control gate electrode.
FIG. 1
shows one unit forming part of the memory cell array.
FIG. 2
is a cross sectional view taken along the line II—II of FIG.
1
.
FIG. 3
is a cross sectional view taken along the line III—III of FIG.
1
.
A field oxide film
12
formed by the LOCOS method is disposed on a p-type silicon substrate (or p-type well)
11
. An area in which the field oxide film
12
is formed is an element isolation region and an area in which the field oxide film
12
is not formed is an element region.
In the element region, a plurality of memory cells forming the NAND cell lines are disposed. If attention is paid to one NAND cell line, eight memory cells M
1
to M
8
are serially connected in this example. Each memory cell includes a gate insulating film
13
on the silicon substrate
11
, a floating gate electrode
14
on the gate insulating film
13
, an insulating film
15
on the floating gate electrode
14
, and a control gate electrode
16
on the insulating film
15
. Each memory cell includes n-type diffusion layers
19
acting as source and drain regions. The n-type diffusion layer
19
in the NAND cell line is commonly used by two adjacent memory cells.
A drain side select transistor S
1
is connected between the NAND cell line and the bit line
18
and a source side select transistor S
2
is connected between the NAND cell line and the source line. The select transistors S
1
, S
2
respectively include select gate electrodes
14
,
16
and n-type diffusion layers
19
.
An interlayer insulator
17
covering the memory cells constructing the NAND cell line is formed on the silicon substrate
11
. A contact hole which reaches the n-type diffusion layer (drain) of the select transistor S
1
is formed in the interlayer insulator
17
. The bit line
18
is disposed on the interlayer insulator
17
and connected to the n-type diffusion layer (drain) of the select transistor S
1
via the contact hole.
Control gate electrodes of a plurality of memory cells in one row are integrally formed to construct one word line. The control gate electrodes (word lines) CG
1
, CG
2
, . . . , CG
8
extend in the row direction. The select gate electrodes SG
1
, SG
2
of the select transistors S
1
, S
2
are also extend in the row direction.
FIG. 4
shows an equivalent circuit of the NAND cell line of FIG.
1
.
FIG. 5
shows part of the memory cell array containing a plurality of NAND cell lines.
Source lines
20
extend in the row direction and are connected to the source side nodes of the NAND cell lines via the select transistors S
2
. Reference potential lines
21
extend in the column direction and are arranged with 64 bit lines BL
0
to BL
63
disposed therebetween, for example. Each of the source lines
20
is connected to the reference potential lines
21
in each position where it extends across the 64 bit lines BL
0
to BL
63
, for example. The reference potential lines
21
are connected to peripheral circuits. The control gate electrodes CG
1
to CG
8
of the memory cell and the gate electrodes SG
1
, SG
2
of the select transistors extend in the row direction.
Normally, a set of memory cells connected to one control gate electrode (word line) is called one page and a set of pages (in this example, 8 pages) disposed between the drain side select transistor S
1
and the source side select transistor S
2
is called one NAND block or simply one block.
For example, one page is constructed by memory cells of 256 bytes (256×8 bits). Data is almost simultaneously written into the memory cells in one page. One block is constructed by memory cells of 2048 bytes (2048×8 bits). Data is almost simultaneously erased for the memory cells in one block.
The operation of the NAND type flash EEPROM is as follows.
Data writing is effected by sequentially selecting memory cells one by one starting from the memory cell which lies farthest from the bit line to the memory cell which lies nearest to the bit line among the memory cells in the NAND cell line and writing data into the selected memory cell.
A write potential Vpp (for example, approx. 20 V) which is higher than the power supply potential is applied to the control gate electrode of the selected memory cell and an intermediate potential (for example, approx. 10 V) is applied to the control gate electrodes of the non-selected memory cells. Further, an intermediate potential (for example, approx. 10 V) is applied to the gate electrode SG
1
of the drain side select transistor S
1
, and 0 V (“0” writing) or intermediate potential (“1” writing) is applied to the bit line BLi according to the written data.
The potential of the bit line BLi is transmitted to the selected memory cell. In the case of “0” writing, since a high voltage is applied between the floating gate electrode of the selected memory cell and the silicon substrate (channel), electrons move from the silicon substrate to the floating gate electrode by the tunnel effect. If electrons are injected into the floating gate electrode, the threshold value of the memory cell is shifted in the positive direction.
On the other hand, in the case of “1” writing, electrons will not move from the silicon substrate to the floating gate electrode and the threshold value of the memory cell is kept unchanged.
Data erasing is almost simultaneously effected for all of the memory cells in at least one selected block. In the selected block, 0 V is applied to all of the control gate electrodes CG
1
to CG
8
and the gate electrodes SG
1
, SG
2
of the select transistors S
1
, S
2
and a high potential VppE (for example, approx. 20 V) is applied to the n-type substrate and p-type well in which the memory cells are arranged.
As a result, in the memory cells in the selected block, electrons are discharged from the floating gate electrodes to the p-type well to shift the threshold voltage in the negative direction.
In the non-selected block, the high potential VppE is applied to all of the control gate electrodes CG
1
to CG
8
and the gate electrodes SG
1
, SG
2
of the select transistors S
1
, S
2
and the high potential VppE is also applied to the n-type substrate and p-type well in which the memory cells are arranged. Therefore, the threshold values of the memory cell in the non-selected block are kept unchanged.
Data read is almost simultaneously effected for memory cells of one page. After the bit line BLi is set to a precharge potential and set into an electrically floating state, the control gate electrode of the selected memory cell is set to 0 V, the control gate electrodes of the non-selected memory cells are set to a power supply potential Vcc (for example, approx. 3 V), the gate electrodes of the select transistors are set to the power supply potential Vcc, and the source lines are set to 0 V.
At this time, if data in the selected memory cell is “1” (the threshold vth is less than 0 V), the selected memory cell is turned ON. If the selected memory cell is turned ON, the potential of the bit line BLi is lowered. On the other hand, if data of the selected memory cell is “0” (the threshold value exceeds 0 V), the selected memory cell is turned OFF. If the selected memory cell is turned OFF, the potential of the bit line BLi is kept at the precharge potential.
That is, data read of the memory cell is effected by detecting the potential of the bit line BLi by use of a sense amplifier (or a latch circuit having a sense amplifier function).
In the NAND type flash EEPROM described above, a case wherein one sense ampl

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