Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-08-23
2001-10-02
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185280
Reexamination Certificate
active
06297991
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to the structure of a programming circuit in the nonvolatile semiconductor memory device.
(b) Description of the Related Art
Flash memory is known as a typical nonvolatile semiconductor memory device, wherein each memory cell includes a MOSFET having a floating gate for programming of the memory cell.
FIG. 1
shows a conventional flash memory, which includes a programming section
201
, a memory cell array
203
and a selector section
202
. The programming section
201
includes voltage divider
210
including resistors R
21
and R
22
for dividing source potential VPP, an n-channel undoped MOSFET (nMOSFET) Tr
21
having a gate coupled to an output node of the voltage divider
210
. The memory cell array
203
includes a plurality of memory cells arranged in a matrix and each implemented by a single cell transistor Tr
26
. . . Tr
29
. The cell transistor Tr
26
. . . Tr
29
has a source connected to the ground, a drain connected to a corresponding bit line B
21
. . . B
24
extending in the column direction, and a gate connected to a corresponding word line W
2
extending in the row direction. The selector section
202
includes a plurality of p-channel MOSFETs (pMOSFETs) Tr
22
to Tr
25
each corresponding to a bit line B
21
. . . B
24
for selection thereof.
The potential of node C
2
connecting the resistors R
1
and R
2
together is applied as a reference potential to the gate of nMOSFET Tr
21
, which delivers a programming voltage from the source through node A
2
. Since the undoped nMOSFET Tr
21
has a threshold voltage of zero volt, the potential of node A
2
is substantially equal to the reference potential at node C
2
.
In a programming operation of a cell transistor Tr
26
, for example, a high voltage is applied to the word line W
2
, and the gate potential Y
21
of pMOSFET Tr
22
is set below the potential of node A
2
minus the absolute value of the threshold voltage VTP
2
of pMOSFET Tr
22
to turn on the pMOSFET Tr
22
, whereby the drain of the cell transistor Tr
26
is applied with the programming voltage. Thus, cell transistor Tr
26
is turned on to pass the drain current, whereby hot electrons are generated in the vicinity of the drain of the cell transistor Tr
26
to be injected into the floating gate of the cell transistor Tr
26
for programming. At this stage, although the potential of node A
2
is lowered by a product of the on-resistance of the undoped nMOSFET Tr
21
and the drain current of the cell transistor Tr
26
, the potential of node A
2
resides substantially at the specified setting voltage due to the small on-resistance of the undoped nMOSFET Tr
21
, whereby a desired programming speed is obtained.
Assuming that the undoped nMOSFET Tr
21
operates in a saturated state, the drain current Ids thereof is expressed by:
Ids=
(1/2)&bgr;(
W/L
)
Vgs
2
.
wherein &bgr;, W, L and Vgs are a constant, gate width, gate length and the source-to-gate voltage of the undoped nMOSFET. The drain current Ids is set at a maximum programming current and &bgr; is determined by the fabrication process. The potential of node A
2
is determined as the desired programming voltage for programming the cell transistors. Since the source-to-gate voltage Vgs is equal to the potential of node C
2
minus the potential of node A
2
, the ratio of W/L for the undoped nMOSFET Tr
21
can be determined based on the maximum drain current or the maximum programming current.
On the other hand, in a programming operation for a row or group of the cell transistors Tr
26
to Tr
29
at a time, the potential of word line W
2
is set at a high voltage, the potentials Y
21
to Y
24
of the gates of pMOSFETs Tr
22
to Tr
25
are set below the potential of node A
2
minus the absolute value of the threshold voltage VTP
2
of pMOSFETs Tr
22
to Tr
25
to turn on the pMOSFETs Tr
22
to Tr
25
, whereby the drains of the cell transistors Tr
26
to Tr
29
are applied with the programming voltage.
Thus, cell transistors Tr
26
to Tr
29
are turned on to pass the drain currents, whereby hot electrons are generated in the vicinities of the drains of the cell transistors Tr
26
to Tr
29
to be injected into the floating gates of the cell transistors Tr
26
to Tr
29
for programming.
FIG. 2
shows the potential of node A
2
at this stage as well as the potentials of other nodes. The potential of node A
2
is lowered by a product of the on-resistance of undoped nMOSFET Tr
21
and the sum IWO of the drain currents of the cell transistors Tr
26
to Tr
29
. The reduction of the potential of node A
2
by Vgs with respect to the potential of node C
2
causes that the programming voltage is lower than the critical voltage WX which allows safe programming of the cell transistor.
More specifically, although the on-resistance of the undoped nMOSFET Tr
21
is set at a low value, the potential of node A
2
is lowered below the critical voltage due to the drain currents of the cell transistors Tr
26
to Tr
29
. This lowers the programming speed of the cell transistors Tr
26
to Tr
29
compared to the case of programming of the single cell transistor Tr
26
. This may be called an inherent problem involved in the output voltage supplied from a source follower scheme.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device which is capable of being programmed substantially without lowering the programming speed in the case of programming a plurality of cell transistors at a time compared to a case of programming a single cell transistor.
The present invention provides a nonvolatile semiconductor memory device including a memory cell array having an array of nonvolatile memory cells each including a cell transistor, a bit line disposed for each column of the memory cells for supplying source current to the cell transistors of a corresponding column of the memory cells, a word line disposed for each row of the memory cells for activating the cell transistors of a corresponding row of the memory cells, a selector section for selecting one or plurality of the memory cells for programming, and a programming section including a programming transistor having an output node for supplying programming current to the bit lines, the output node assuming a substantially constant potential irrespective of a number of the memory cells being programmed at a time.
In accordance with the present invention, since the potential of the output node of the programming section is maintained substantially at a constant irrespective of the number of memory cells being programmed at a time, the programming speed can be maintained substantially constant.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 5519656 (1996-05-01), Maccarrone et al.
patent: 5706240 (1998-01-01), Fiocchi et al.
patent: 5748534 (1998-05-01), Dunlap et al.
patent: 6111791 (2000-08-01), Ghilardelli
NEC Corporation
Phung Anh
Zarabian Amir
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