Nonvolatile semiconductor memory circuit utilizing a MIS...

Details Nonvolatile semiconductor memory circuit utilizing a MIS... Nonvolatile semiconductor memory circuit utilizing a MIS...

2008-06-18

2010-10-26

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read only systems

Semiconductive

C365S103000, C365S154000, C365S190000, C365S189050, C365S189070

Reexamination Certificate

active

07821806

ABSTRACT:
A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

REFERENCES:
patent: 3636530 (1972-01-01), Mark et al.
patent: 4419744 (1983-12-01), Rutter
patent: 5956269 (1999-09-01), Ouyang et al.
patent: 6038168 (2000-03-01), Allen et al.
patent: 6064590 (2000-05-01), Han et al.
patent: 6740927 (2004-05-01), Jeng
patent: 6906953 (2005-06-01), Forbes et al.
patent: 6906962 (2005-06-01), Layman et al.
patent: 6909635 (2005-06-01), Forbes et al.
patent: 7227234 (2007-06-01), Roizon et al.
patent: 7733714 (2010-06-01), Horiuchi et al.
patent: 2004/0232477 (2004-11-01), Iwata et al.
patent: 2004/0252554 (2004-12-01), Fournel et al.
patent: 2009/0310428 (2009-12-01), Horiuchi et al.
patent: 06-076582 (1994-03-01), None
patent: 06-231587 (1994-08-01), None
patent: 2001-156188 (2001-06-01), None
patent: 2002-237540 (2002-08-01), None
patent: WO2004/057621 (2004-07-01), None
patent: WO2006/093629 (2006-09-01), None

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