Nonvolatile semiconductor memory circuit including dummy sense a

Details Nonvolatile semiconductor memory circuit including dummy sense a Nonvolatile semiconductor memory circuit including dummy sense a

1986-03-24

1987-06-30

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

365210, 323313, G11C 1140

Patent

active

046775900

ABSTRACT:
A nonvolatile semiconductor memory circuit is provided with a plurality of bit lines and a plurality of word lines. The nonvolatile semiconductor memory cells are located at intersections of the bit lines and word lines and formed by MOS transistors having a floating gate and a control gate therein. A bias circuit supplies a read-out voltage to the control gate of the selected nonvolatile semiconductor memory cell. Sense amplifiers are also included, each having an input which receives read-out data from the selected nonvolatile semiconductor memory cell, and an output which outputs amplified read-out data.
A bias circuit is formed by a dummy cell having the same construction as the nonvolatile semiconductor memory cells. A dummy sense amplifier is included having the same construction as the sense amplifiers. A voltage setting circuit is also included, having feedback circuitry connected between the output of the voltage setting circuit and the control gate of the MOS transistor in the dummy cell. Further, in the present invention, depletion-type MOS transistors are used for coupling the gate of the MOS transistor to the bias circuit.

REFERENCES:
patent: 4063224 (1977-12-01), Kirschner
patent: 4099264 (1978-07-01), Lodi
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4266283 (1981-05-01), Perlegos et al.
patent: 4301535 (1981-11-01), McKenney et al.
patent: 4404659 (1983-09-01), Kihara et al.
patent: 4527256 (1985-07-01), Giebel
Hagiwara et al., "A 16K Bit Electrically Erasable PROM Using n--Channel Si--Gate MNOS Technology", IEEE Jour. of Solid State Circuits, vol. SC--15, No. 3, Jun. 1980, pp. 346-353.
Schanzer, "Read Voltage Supply for MNOS Memory Arrays", RCA Technical Notes, No. 1233, Oct. 26, 1979, pp. 1-4.
Kelley et al., "An Electrically Alterable ROM--and It Doesn't Use Nitride", Electronics, vol. 49, No. 25, Dec. 9, 1976, pp. 101-104.

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory circuit including dummy sense a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory circuit including dummy sense a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory circuit including dummy sense a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-451781