Nonvolatile semiconductor memory cell capable of saving overwrit

Static information storage and retrieval – Floating gate – Particular biasing

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36518517, 36518522, 36518524, G11C 1134

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active

059177560

ABSTRACT:
If data is read from a selected memory cell at the time of overwrite verifying, a potential of a bit line is changed in accordance with data. If a transistor is turned on, a latch circuit is set in accordance with data of the bit line. In a case where there is a memory cell being in an overwrite state, data of the selected memory cell is latched to the latch circuit, and data corresponding to one page is erased. Thereafter, a normally writing operation is executed by data latch to the latch circuit, thereby the memory cell being in the overwrite state can be used as a normal threshold voltage.

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Shin-Ichi Kobayashi et al: "Memory Array Architecture and Decoding Cheme for 3V Only Sevtor Erasable Dinor Flash Memory," Proceedings of the Symposium on VLSI Circuits, Kyoto, May 19-21, 1993, May 19, 1993, Institute of Electrical and Electronics Engineers, pp. 97-98.

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