Nonvolatile semiconductor memory array with byte-program,...

Details Nonvolatile semiconductor memory array with byte-program,... Nonvolatile semiconductor memory array with byte-program,...

2005-05-03

2005-05-03

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185130, C365S185110, C365S185160, C365S185180, C365S185020, C365S185290

Reexamination Certificate

active

06888754

ABSTRACT:
This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

REFERENCES:
patent: 5774412 (1998-06-01), Raad et al.
patent: 5812452 (1998-09-01), Hoang
patent: 6011746 (2000-01-01), Oh
patent: 6088269 (2000-07-01), Lambertson
patent: 6128220 (2000-10-01), Banyai et al.
patent: 6201732 (2001-03-01), Caywood
patent: 6646950 (2003-11-01), Akaogi

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