Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2006-12-12
2006-12-12
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185230, C365S185240, C365S189050, C365S230040, C365S230080
Reexamination Certificate
active
07149116
ABSTRACT:
A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.
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Arai Fumitaka
Matsunaga Yasuhiko
Sakuma Makoto
Shirota Riichiro
Elms Richard
Kabushiki Kaisha Toshiba
Luu Pho M.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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