Static information storage and retrieval – Floating gate
Reexamination Certificate
2006-04-11
2006-04-11
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Floating gate
C365S185140, C365S185260
Reexamination Certificate
active
07027329
ABSTRACT:
A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.
REFERENCES:
patent: 5453955 (1995-09-01), Sakui et al.
patent: 8-167291 (1996-06-01), None
patent: 8-329700 (1996-12-01), None
patent: 11-176164 (1999-07-01), None
patent: 11-297080 (1999-10-01), None
patent: 2001-168306 (2001-06-01), None
patent: 2002-279788 (2002-09-01), None
Arai Fumitaka
Matsunaga Yasuhiko
Sakuma Makoto
Shirota Riichiro
Luu Pho M.
Nguyen Van Thu
LandOfFree
Nonvolatile semiconductor memory and programming method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory and programming method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory and programming method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3547368