Nonvolatile semiconductor memory and its test method

Details Nonvolatile semiconductor memory and its test method Nonvolatile semiconductor memory and its test method

2005-05-24

2005-05-24

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185220, C365S185290, C365S185300

Reexamination Certificate

active

06898119

ABSTRACT:
A nonvolatile semiconductor memory is disclosed, which comprises a nonvolatile memory cell array, a write circuit which repeatedly executes a write and a verification, and a write voltage control circuit, the write voltage control circuit comprising a first binary counter which counts a first clock signal supplied every time the verification fails and supplies output data to the write circuit, a first register which stores data for setting the number of erases and verifications, a second binary counter which is reset using a first timing, counts a second clock signal supplied if a verify write executed on the target write unit fails, an accumulative value storage circuit which is reset using a second timing and stores a value corresponding to an accumulative value for the contents of the second binary counter, and a nonvolatile storage element which stores the appropriate value for the write start voltage.

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K. Imamiya, et al., IEEE Journal of Solid-State Circuits, vol. 34, No. 11, pp. 1536-1543, “A 130-nmw, 256-Mbit NAND Flash With Shallow Trench Isolation Technology”, Nov. 1999.
K-D. Suh, et al., ISSCC95/Session 7/Flash Memory/Paper TA 7.5, Digest of Technical Papers, pp. 128-129, A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme, Feb. 16, 1995.

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