Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-07-11
2004-10-19
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185090, C365S185290, C365S185300
Reexamination Certificate
active
06807102
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-204442, filed Jul. 12, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and its test method, and in particular, to a circuit that sets an initial value for a write voltage and an initial value for an erase voltage both of which are used for a nonvolatile semiconductor memory that carries out verify writes and verify erasures, as well as a test method for this circuit. The present invention is applicable to, for example, a NAND type flash memory.
2. Description of the Related Art
A NAND type flash memory, a kind of nonvolatile semiconductor memory, has been published in documents such as “K. Imamiya et. al. “A 130-mm
2
256-Mb NAND Flash with Shallow Trench Isolation Technology”, IEEE J. Solid State Circuits, Vol. 34, pp. 1536-1543, Bov. 1999”.
For such a nonvolatile semiconductor memory, voltage trimming and the redundancy repair of bad cells are carried out during a wafer test sequence.
FIG. 15
is a flow chart showing schematically a wafer test sequence for a conventional NAND type flash memory.
Description will be given of operations performed during the sequence.
In a DC test, contact checks and DC checks for a standby current or the like are conducted. In Vref (reference voltage) trimming, the reference voltage Vref of each chip on a wafer is monitored. Then, a trimming value is calculated which is required to correct the monitored reference voltages to a target value.
Then, Vpgm (write voltage) initial value trimming is carried out. An incremental step pulse programming scheme is employed for the NAND type flash memory to increase a write voltage Vpgm step by step starting with its initial value. This method is described in, for example, “K. D. Suh et. al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, ISSCC Digest of Technical Papers, pp. 128 to 129, February 1995”.
This write method requires the initial value of Vpgm to be optimized so that a write time (or the number of write loops) does not exceed a predetermined time (the number of times). To achieve this, it is necessary to find a block (good block) in a memory cell array on which a write and erasure can be successfully executed. This is because bad cells have not been subjected to a redundancy repair yet.
When a good block is found, the optimum value is determined by executing a write on this block while varying the initial value of Vpgm.
Subsequently, a phase cut for voltage trimming is carried out. During this step, the wafer is transferred to a laser blow apparatus and a phase cut is executed in accordance with the trimming value determined by the Vref trimming and the Vpgm initial value trimming.
Subsequently, bad columns and rows are detected. In this case, bad columns and rows are detected by writing several data patterns in the memory cell array for a redundancy repair.
Then, a redundancy phase cut is carried out. In this case, the wafer is transferred to the laser blow apparatus again and a phase cut for a redundancy repair is executed.
In this flow chart, the phase cut for voltage trimming is carried out before the detection of bad columns and rows because if the detection of bad columns and rows is executed with incorrect internally generated voltages such as Vpgm, it may be impossible to find defects.
The time required for a wafer test sequence such as the one described above is reflected in the cost of the chip. Accordingly, in order to reduce the chip cost, it is necessary to minimize the test time while conducting required tests.
In the above described wafer test sequence, a factor relating to an increased test time is the presence of the phase cut step. Before carrying out a phase cut using a laser blow, the wafer must be removed from the tester and then transferred to the laser blow apparatus. This results in a temporal overhead. In particular, in the above described wafer test sequence, two phase cuts must be executed. Consequently, the overhead is more marked.
The applicant's Jpn. Pat. Appln. KOKAI Publication No. 2001-176290 (Jpn. Pat. Appln. No. 11-351396) “Nonvolatile Semiconductor Device” describes a method of reducing the time required for the phase cut steps.
Further, the applicant has proposed in Jpn. Pat. Appln. KOKAI Publication No. 2002-117699 (Jpn. Pat. Appln. No. 2000-303854) “Nonvolatile Semiconductor Device” that a memory cell array stores information on a trimming value for a write voltage/erase voltage as well as redundancy which information be used for a nonvolatile semiconductor memory is stored in a memory cell array and that when the memory is powered on, the information be retrieved from the memory cell array and stored in a predetermined register, so that when the memory is in a normal operational state, the information on the voltage trimming value and redundancy is stored in this register.
However, in the NAND type flash memory, the initial write or erase voltage is determined on the basis of the results of a test conducted for each chip. Detailed description will be given below of problems with this determination.
FIG. 9
schematically shows a related configuration in order to describe a read/write operation performed by the NAND type flash memory.
In
FIG. 9
, a memory cell array
11
is composed of NAND cell units arranged in a column direction and a row direction to form a matrix. Each of the NAND cell units is comprised of electrically rewritable nonvolatile memory cells connected in series. Each of the memory cells has a stacked gate type MOS transistor structure in which a control gate and a floating gate are stacked.
The memory cell array
11
is formed on a well area insulated and separated from the other components. To erase data from a memory cell in the memory cell array
11
, the following erase method is employed: an erase operation is divided into a plurality of steps so that an erase voltage applied to the well area is increased in increments of a specified value in each step starting with an initial voltage.
The memory cell array
11
is provided with a plurality of word lines and bit lines that cross one another. The plurality of word lines are selectively driven by a decoder output from a row decoder
12
.
When data is read, a signal read from a memory cell in the memory cell array
11
is supplied to a page buffer
13
via a bit line. The signal is then sensed in the page buffer
13
, and then outputted in unit of column to equipment located outside the chip.
When data is written, a voltage corresponding to externally supplied write data is supplied to a bit line via a page buffer
13
and the data is then written in a selected memory cell.
Word lines in the memory cell array
11
connect a plurality of NAND cell units together. The plurality of NAND cell units constitute a cell block, the minimum unit for a data erasure. A plurality of cell blocks are arranged via common bit lines.
The range of memory cells selected by one word line is called “one page”. A data write operation is performed on the entire page at a time. For example, write data retained in a data register for 512 bytes is written at a time through a bit line.
FIGS. 10A and 10B
show a bias relationship observed when data is written in a memory cell (cell transistor) of the NAND type flash memory.
As shown in
FIG. 10A
, if write data is “0”, a write bias (in this example, 0V) is applied to a well area in a cell transistor. Such a cell transistor to which the write bias is applied has a threshold being shifted to the positive side because electrons are injected into a floating gate (writes are carried out).
As shown in
FIG. 10B
, if write data is “1”, a write bias is not applied to a well area in a cell transistor, to establish a floating state. Such a cell transistor to which the write bias is not applied maintains a low threshold because no elect
Imamiya Kenichi
Kawai Koichi
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Yoha Connie C.
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