Nonvolatile semiconductor memory, a data write-in method for...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185090, C365S185280

Reexamination Certificate

active

07317636

ABSTRACT:
A nonvolatile semiconductor memory includes a memory cell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of repeating data write-in and program verification, a bit scan circuit that is connected to the page buffer and determines whether or not the number of fail bits is equal to or less than number of reference bits based on the program verification results retained in the page buffer, a register that is connected to the bit scan circuit and retains determination results of the bit scan circuit, and a sequencer that controls the write-in operation and an operating sequence of the bit scan circuit and terminates the write-in operation while leaving the number of fail bits in response to the results temporarily stored in the register.

REFERENCES:
patent: 6507518 (2003-01-01), Hosono et al.
patent: 6657896 (2003-12-01), Hosono et al.
patent: 6859401 (2005-02-01), Ikehashi et al.
patent: 6868009 (2005-03-01), Hung et al.
patent: 6922366 (2005-07-01), Micheloni et al.
patent: 2005/0041515 (2005-02-01), Futatsuyama et al.
patent: 2002-140899 (2002-05-01), None
patent: 2002-216486 (2002-08-01), None

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