Nonvolatile semiconductor memory

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185110, C365S185120

Reexamination Certificate

active

07110320

ABSTRACT:
Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

REFERENCES:
patent: 4924437 (1990-05-01), Paterson et al.
patent: 4953129 (1990-08-01), Kobayashi et al.
patent: 5053648 (1991-10-01), van den Elshout et al.
patent: 5060195 (1991-10-01), Gill et al.
patent: 5168335 (1992-12-01), D'Arrigo et al.
patent: 5222040 (1993-06-01), Challa
patent: 5249158 (1993-09-01), Kynett et al.
patent: 5280454 (1994-01-01), Tanaka et al.
patent: 5297103 (1994-03-01), Higuchi
patent: 5347490 (1994-09-01), Terada et al.
patent: 5363330 (1994-11-01), Kobayashi et al.
patent: 5392253 (1995-02-01), Atsumi et al.
patent: 5396459 (1995-03-01), Arakawa
patent: 5530828 (1996-06-01), Kaki et al.
patent: 5663901 (1997-09-01), Wallace et al.
patent: 5828600 (1998-10-01), Kato et al.
patent: 6201735 (2001-03-01), Kato et al.
patent: 6335880 (2002-01-01), Kato et al.
patent: 6510086 (2003-01-01), Kato et al.
patent: 61-127179 (1986-08-01), None
patent: 62-276878 (1987-12-01), None
patent: 62-298096 (1987-12-01), None
patent: 01-229497 (1989-09-01), None
patent: 02-040199 (1990-02-01), None
patent: A-2-044599 (1990-02-01), None
patent: 02-260455 (1990-10-01), None
patent: 03-066171 (1991-03-01), None
patent: 03-219496 (1991-09-01), None
patent: 03-250495 (1991-11-01), None
patent: 04-007870 (1992-01-01), None
patent: 04-014871 (1992-01-01), None
IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1999, pp. 484-491.
IEEE Journal of Solid State Circuits, vol.SC-17, No. 5, Oct. 1982, pp. 821-827.
Kume et al, H., “A 1.28 μm2Contactless Memory Cell Technology for a 3-V Only 64 Mbit EEPROM”,International Electron Devices Meeting, 1992, Technical Digest, pp. 24.7.1-24.7.3.
Nakayama et al, T., “A 60ns 16Mb Flash EEPROM with Program and Erase Sequence Controller”, 1991 IEEE ISSCC, pp. 260-261.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Nonvolatile semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3587342

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.