Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2006-03-28

2006-03-28

Tran, Michael T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180

Reexamination Certificate

active

07020025

ABSTRACT:
A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.

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