Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2003-04-02

2004-08-10

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185010, C365S210130

Reexamination Certificate

active

06775185

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory including a nonvolatile memory section and a buffer section thereof and particularly to a technique to realize high speed access with interleave operation by utilizing the nonvolatile memory section and the buffer section, for example, the technique which may be utilized effectively to a flash memory.
The Japanese Patent Application Publication No. Hei 11(1999)-85609 describes a flash memory including a nonvolatile memory section and a buffer section thereof. According to this flash memory, the memory section can read or write data only in the unit of 8-bit or 16-bit and the buffer section provided is tacitly used to execute commands of erase, write and read operations for the flash memory because it is required to perform exchange of data in unit of single sector or a plurality of sectors such as 512 bytes in a host device.
Moreover, the Japanese Patent Application Publication Nos. 2001-28428 (U.S. Pat. No. 6,438,028) and 2002-197876 (U.S. Publication No. US-2002-0114192-A1) describe a flash memory utilizing an assist gate (AG) for separation of elements thereof. When the assist gate (AG) is used for separation of elements in the flash memory, a source and a drain can be used in common. In this case, since the source and drain locations are replaced with each other as required for the write and read operations, it is required to set the memory cells in every other cell an the operation object for many cells provided in parallel using in common the word line thereof. In short, since the adjacent memory cells use in common the source line and bit line connected to the source and drain, an operation error is generated when the adjacent memory cells are operated in parallel. Accordingly, the write and read operations to the flash memory described above using in common the word line have to be performed individually in the flash memories of the even numbers and that of the odd numbers.
SUMMARY OF THE INVENTION
The inventors of the present invention have discussed this point and found following problem. When the write and read operations are conducted continuously, information stored in the memory cells of even numbers is read to the buffer section from the memory section for the memory cells connected to only one word line, information in the buffer section is then outputted to the external side, thereafter information stored in the memory cells of the odd numbers is read to the buffer section from the memory section, and information in the buffer section is outputted to the external side. There is provided the buffer section which can store temporarily the information of one word line and operations must be separated perfectly for the memory cells of the even numbers and odd numbers. The situation is exactly the same in the case of the write operation and this situation will impede high speed access operation. This problem results not only from the reason that access is separated for the memory cells of the even numbers and odd numbers in the 4-level flash memory but also from the restriction on the selection scale of memory cells in the 2-level flash memory and storage capacity of buffer section.
An object of the present invention is to provide a semiconductor memory which can realize high speed write and read access to and from a nonvolatile memory section.
Another object of the present invention is to provide a semiconductor memory which can reduce overhead in the data transfer between the external side and the nonvolatile memory section.
The aforementioned and the other objects and novel features of the present invention will become apparent from the following description of this specification and the accompanying drawings.
Typical inventions among those disclosed in this specification will be briefly described as follows.
[1] <<Doubled Buffer Size of Access Unit>>
According to a first aspect, the semiconductor memory of the present invention includes a plurality of memory banks and control sections and each memory bank includes a plurality of nonvolatile memory sections which can update stored information and a pair of buffer sections which can respectively store the information in unit of write and read operation of the nonvolatile memory section. The control section performs, in response to an instruction for access operation, data transfer between one buffer section of the memory bank and the nonvolatile memory section and is also capable of controlling interleave operation for data transfer between the other buffer section of the relevant memory bank and the external side. The nonvolatile memory section is configured, for example, with a flash memory section.
From the above description, since the operation to transfer the data read from the nonvolatile memory section to one buffer section and the operation to output the read data transferred to the other buffer section to the external side are performed in parallel in the read operation, high speed read operation can be realized in comparison with the case where the serial operation that data read from the nonvolatile memory section is transferred to the buffer section and this data is then outputted to the external side from the relevant buffer section is sequentially performed. This process can also be applied to the write operation. In this write operation, since the operation to transfer the write data to one buffer section from the external side and the operation to transfer the write data already transferred to the other data buffer to the nonvolatile memory section are performed in parallel, high speed write operation can be realized in comparison with the case where the serial operation that the write data is transferred to the buffer section from the external side and this data is then transferred to the nonvolatile memory section is sequentially performed.
As a practical profile of the present invention, the nonvolatile memory section includes a plurality of memory cells which are allocated in a matrix, a plurality of memory cells include in common a word line in every predetermined number, and in the control section, a part of the memory cells and the remainders using in common the word line are individually considered as the objects of access operation in the write and read access operations. For example, the control section individually considers the memory cells of the even numbers and odd numbers among those using in common the word line as the objects of the write access operation and read access operation.
In this case, the control section is capable of realizing in parallel the operation, in response to an instruction of the read access operation, to control one buffer section corresponding to respective nonvolatile memory section to transfer in parallel the read data by causing the plural nonvolatile memory sections to perform in parallel the data read operation and the operation to sequentially select the other buffer sections to cause these buffer sections to output the read date stored therein to the external side. Moreover, the control section is also capable of realizing in parallel the operation, in response to an instruction of the write access operation, to sequentially select one buffer section to transfer the write data from the external side and the operation to write the data by transferring in parallel the write data to the corresponding nonvolatile memory section from the plural buffer sections.
[2] <<Buffer Size Equal to Access Unit>>
According to a second aspect, the semiconductor memory of the present invention includes a plurality of memory banks and a control section. Each memory bank includes a plurality of nonvolatile memory sections which can update stored information and a buffer section which can store information of the write unit and read unit of the nonvolatile memory section. The control section enables use of the buffer sections of the relevant memory bank and the other two memory banks for the operation of one memory bank instructed as the access

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