Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2003-04-23
2004-10-19
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S189050, C365S189120
Reexamination Certificate
active
06807096
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-377054, filed Dec. 26, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory particularly used for a multi-level NAND cell type flash memory, for example, 4-level NAND cell type flash memory.
2. Description of the Related Art
In a multi-level NAND cell type flash memory, in a reading operation, for example, data of one page simultaneously read from a memory cell array are latched at a latch circuit, and then serially accessed bit by bit to be serially outputted to the outside of a chip. In a program operation, for example, data of one page serially inputted to the inside of the chip are serially accessed to be latched bit by bit at the latch circuit, and then the data are simultaneously programmed in the memory cell array (see U.S. Pat. No. 6,331,945B1).
Hereinafter, “serial access” means the above serial accessing, and “serial access time” means a time necessary for this serial accessing operation.
Assuming that the number of memory cells constituting the memory cell array is constant, when n (n is a natural number of 2 or higher) bits, i.e., 2
n
levels, are stored in one memory cell, a memory capacity can be increased by n times compared with a case of storing one bit, i.e., 2 levels, in one memory cell.
However, in a conventional multi-level NAND cell type flash memory, when one bit of n bits stored in one memory cell is randomly read/written, it is necessary to carry out a logical operation for this one bit and the other bits. A time for this operation is increased in proportion to n.
Accordingly, when n bits are stored in one memory cell, compared with the case of storing one bit in one memory cell, time necessary for reading/writing, specifically, time from detection of a reading/writing command to a start of serial accessing (called “1st access time” because it means a time before access to first one bit of one page data) is made longer in proportion to n.
Such long 1st access time is not a big problem when the multi-level NAND cell type flash memory is used as a file memory. It is because for the purpose of simultaneously processing a large amount of data, an increase of a memory capacity is more important than shortening of the 1st access time.
However, when the multi-level NAND cell type flash memory is used as a mixed memory (memory mixed in a logic LSI or the like) which does not need a large memory capacity, high-speed reading/writing is required. Thus, achievement of high speeds for the serial access time and the 1st access time becomes extremely important.
A reason is as follows. For example, even when serial accessing and a reading/writing operation is concurrently carried out to realize high-speed reading/writing, if the 1st access time becomes longer than the serial access time due to multiple levels, for example, the reading/writing operation cannot be finished within the period of the serial accessing. Consequently, a reading/writing speed is limited by the 1st access time.
Thus, in order to realize high-speed reading/writing, achievement of high speeds for both of the serial access time and the 1st access time is important.
Therefore, it is hoped that a data circuit (reading/writing circuit) capable of setting the 1st access time of the multi-level memory substantially equal to that of a binary flash memory will be developed.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a nonvolatile semiconductor memory comprises: a memory cell to store n (n is a natural number of 2 or higher) bits; a first latch section to temporarily store 1 bit among the n bits in a first reading operation; and a second latch section to temporarily store the other 1 bit among the n bits in a second reading operation when the 1 bit has a first value, and in a third reading operation when the 1 bit has a second value.
According to a second aspect of the present invention, a nonvolatile semiconductor memory comprises: a memory cell to store 2 bits; a first latch section to temporarily store 1 bit of the 2 bits in a first reading operation; and a second latch section to temporarily store the other 1 bit of the 2 bits in a second reading operation when the 1 bit has a first value, and in a third reading operation when the 1 bit has a second value.
According to a third aspect of the present invention, a nonvolatile semiconductor memory comprises: a memory cell to store n (n is a natural number of 2 or higher) bits; a first latch section to temporarily store 1 bit among the n bits in a first writing operation; a second latch section to temporarily store the other 1 bit among the n bits in second and third writing operations; and a third latch section to store the other 1 bit in the second writing operation when the 1 bit has a first value, and in the third writing operation when the 1 bit has a second value.
According to a fourth aspect of the present invention, a nonvolatile semiconductor memory comprises: a memory cell to store 2 bits; a first latch section to temporarily store 1 bit of the 2 bits in a first writing operation; a second latch section to temporarily store the other 1 bit of the 2 bits in second and third writing operations; and a third latch section to store the other 1 bit in the second writing operation when the 1 bit has a first value, and in the third writing operation when the 1 bit has a second value.
According to a fifth aspect of the present invention, a nonvolatile semiconductor memory comprises: memory cells to store n (n is a natural number of 2 or higher) bits; sub-data circuits disposed corresponding to the memory cells to carry out a reading/writing operation for the memory cells; and a first shift register to sequentially select the sub-data circuits one by one, wherein each of the sub-data circuits has a first latch section to temporarily store 1 bit among the n bits, and the 1 bit is serially outputted from the first latch section of the sub-data circuit selected by the shift register.
According to a sixth aspect of the present invention, a read method of a nonvolatile semiconductor memory is applied to a memory cell which stores 2 bits by 0, first, second and third threshold levels (0 threshold level<first threshold level<second threshold level<third threshold level). This method comprises the steps of: carrying out a first reading operation for the memory cell by applying a first reading potential between the first threshold level and the second threshold level to a selected word line; determining that 1 bit of the 2 bits has a first value when a threshold value of the memory cell is the 0 or first threshold level; determining that the 1 bit has a second value when a threshold value of the memory cell is the second or third threshold level; then (1) if the 1 bit has the first value, carrying out a second reading operation for the memory cell by applying a second reading potential between the 0 threshold level and the first threshold level to the selected word line, determining that the other 1 bit of the 2 bits has a first value when a threshold value of the memory cell is the 0 threshold level, and determining that the other 1 bit has a second value when a threshold value of the memory cell is the first threshold level; and (2) if the 1 bit has the second value, carrying out a third reading operation for the memory cell by applying a third reading potential between the second threshold level and the third threshold level to the selected word line, determining that the other 1 bit has a first value when a threshold value of the memory cell is the second threshold level, and determining that the other 1 bit has a second value when a threshold value of the memory cell is the third threshold level (an order of (1) and (2) may be reversed).
According to a seventh aspect of the present invention, a program method of a
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Lam David
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