Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2001-05-21

2003-02-18

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S195000, C365S185180

Reexamination Certificate

active

06522583

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-150256, filed May 22, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to the write operation of a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory represented by a NAND flash memory, which has a cell unit formed from a memory cell and select gate transistor.
FIG. 1
is a block diagram showing main part of a conventional NAND flash memory.
A memory cell array
11
has a plurality of cell units laid out in an array. Each cell unit is formed from a NAND array including a plurality of memory cells connected in series and two select gate transistors respectively connected to the two terminals of the NAND array, as is known.
On the memory cell array
11
, word lines WL run in the row direction, and bit lines BL run in the column direction. The word lines WL are connected to a row decoder
12
. The bit lines BL are connected to a sense amplifier
15
having a latch function for temporarily storing write data or read data. The sense amplifier is connected to an I/O buffer
14
through a column gate (column selecting switch)
13
.
The column gate
13
is controlled by the output signal from a column decoder
16
. A boost circuit
19
generates voltages necessary for write, erase, and read modes. For example, in the write mode, the boost circuit
19
generates a program potential Vpgm and applies it to the row decoder
12
.
A row address signal is input to the row decoder
12
. A column address signal is input to the column decoder
16
. A control circuit
21
controls the operation of the row decoder
12
, column gate
13
, and column decoder
16
in accordance with the operation mode. For example, in the write mode, the control circuit
21
controls the switching timing of a potential to be applied to the word line WL (control gate line) or select gate line.
FIG. 2
is a block diagram showing the circuit arrangement of the memory cell array
11
shown in FIG.
1
.
In this example, a cell unit is formed from a NAND array including four memory cells connected in series and two select gate transistors respectively connected to the two terminals of the NAND array.
The drain-side terminal of each cell unit is connected to a bit line BLj (j=0, 1, . . . ). Each bit line BLj is connected to a sense amplifier S/A having a latch function through a high voltage type MOS transistor. A control signal BLTR is input to the gate of the high voltage type MOS transistor. The source-side terminal of each cell unit is connected to a source line common to all cell units.
The group of memory cells connected to one word line (control gate line) WLi (i=0, 1, 2, 3) is normally called a page. One page is a unit of memory cells that are simultaneously write- or read-accessed in, e.g., a data write mode or data read mode for reading data from the memory cells to the sense amplifiers. To read data from the chip to the outside, the data of one page in the sense amplifiers are serially read from the chip to the outside in units of bits or in units of a plurality of bits.
The group of memory cells connected to a plurality of (four, in this example) word lines WL
0
, WL
1
, WL
2
, and WL
3
between two select gate lines is normally called a block. One block is a unit of memory cells for which the erase is simultaneously executed in, e.g., a data erase mode. An erase mode executed for each block is called a block erase mode, and an erase mode executed for all blocks is called a chip erase mode.
The basic operations of the NAND flash memory, i.e., erase, write and read operations will be described next briefly.
Table 1 shows the potential relationship in the erase mode. Table 2 shows the potential relationships in the write and read modes.
TABLE 1
Erase
Well
Vera
Word line in
OV
selected block
Word line in
Floating
unselected block
SGD
Floating
SGS
Floating
TABLE 2
Write
Read
Selected
OV
Clamp level
bit line
Unselected
VDD
—
bit line
Selected
Vpgm
OV
word line
Unselected
Vpass
Vread
word line
SGD
VDD/OV
Vread/0V
SGS
OV
Vread/0V
Selected block/Unselected block
In the erase mode, the well is set to an erase potential Vera (e.g., about 20V). All word lines in a selected block (block for which the erase is to be executed) are set to 0V, and all word lines in an unselected block (block for which no erase is to be executed) are set in a floating state.
A drain-side select gate line SGD and source-side select gate line SGS are also set in the floating state.
In the write mode, a selected bit line (bit line to which a memory cell to be write-accessed is connected) is set to 0V. An unselected bit line (bit line to which a write inhibit cell is connected) is set to, e.g., a power supply potential VDD. A selected word line (control gate line) is set to the program potential Vpgm (e.g., about 16V), and an unselected word line is set to an intermediate potential Vpass (e.g., about 8V).
In the selected block, the drain-side select gate line SGD is set to the power supply potential VDD, and the source-side select gate line SGS is set to 0V. In the unselected block, both the drain-side select gate line SGD and source-side select gate line SGS are set to 0V.
The program potential Vpgm may be stepped up by a predetermined amount dV in accordance with the number of times of write.
In the read mode, the bit line is precharged to, e.g., the clamp level of the bit line. After that, a selected word line (control gate line) is set to 0V, and an unselected word line is set to a read potential Vread (e.g., about 3.5V).
For a binary (2-level type) memory, since the threshold value of a “1”-cell is negative (less than 0V), and that of a “0”-cell is positive (more than 0V and less than Vread), all memory cells connected to an unselected word line are turned on. Hence, the potential of the bit line is determined by ON/OFF-controlling the memory cells connected to the selected word line. The change in bit line potential is detected by the sense amplifier having the latch function.
In the selected block, both the drain-side select gate line SGD and source-side select gate line SGS are set to the read potential Vread. In the unselected block, both the drain-side select gate line SGD and source-side select gate line SGS are set to 0V.
Details of the write operation of the NAND flash memory shown in
FIGS. 1 and 2
will be described next.
Assumptions are that the word line WL
2
shown in
FIG. 2
is selected, of the memory cells connected to the word line WL
2
, a memory cell A indicated by a broken line is the selected cell (cell to be subjected to “0”-programming), and the remaining memory cells are unselected cells (cells to be subjected to “1”programming, i.e., write inhibit cell).
FIG. 3
is a waveform chart showing signal waveforms of a first conventional write scheme, i.e., self boost write scheme.
First, write data of one page are input from the outside of the chip to the sense amplifiers S/A (data load). Since “0”-programming (write operation for increasing the threshold value) is to be executed only for the memory cell A, data “0” is input to the sense amplifier S/A connected to a selected bit line BL
2
, and data “1” is input to the sense amplifiers S/A connected to remaining bit lines BL
0
, BL
1
, BL
3
, and BL
4
.
In the NAND flash memory, each sense amplifier S/A has a latch function (latch circuit) for temporarily storing write data. The sense amplifier S/A connected to the selected bit line BL
2
latches the data “0”, and the sense amplifiers S/A connected to the bit lines BL
0
, BL
1
, BL
3
, and BL
4
latch the data “1”.
Referring to the signal waveform chart of
FIG. 3
, BL“0” represents the bit line BL
2
connected to the memory cell A to be subjected to “0”-programming, and BL“1” represents the bit lines BL
0
, BL
1
, BL
3
, and BL
4
connected to cells (write inhibit cells) to be subjected to “1”-programming.
In the write operation, f

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