Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2000-03-16

2001-06-05

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

Reexamination Certificate

active

06243295

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory having a stacked gate structure and, more particularly, to a nonvolatile semiconductor memory used in a NAND flash EEPROM.
A NAND flash EEPROM (Electrically Erasable and Programmable Read Only Memory) is well known as a nonvolatile semiconductor memory which can electrically change program data, and has a memory cell structure suitable for high integration of elements (large memory capacity).
FIG. 1
shows a memory cell array of the NAND flash EEPROM.
FIG. 2
shows an example of the memory cell structure of the NAND flash EEPROM.
The memory cell array of the NAND flash EEPROM comprises a plurality of NAND cell units disposed in a matrix. Each NAND cell unit is constructed by NAND cells each consisting of a series circuit of a plurality of (16 in this case) memory cells, and two select gate transistors respectively connected to the end cells.
The memory cells and select gate transistors in each NAND cell unit are disposed in a p-well
12
in an n-well
11
formed on a p-semiconductor substrate
10
, i.e., in a twin-well.
The memory cells in the NAND cell have a so-called stacked gate structure formed by stacking control gate electrodes CG
0
, . . . , CG
15
on floating gate electrodes FG. Also, the select gate transistors have the same stacked gate structure as that of the memory cells, but only the lower layers serve as gate electrodes SGS and SGD in practice.
The control gate electrodes (word lines) CG
0
, CG
1
, . . . , CG
15
respectively run in the row direction of the memory cell array, and are commonly connected to the memory cells in the same rows. Likewise, the select gate electrodes (select gate lines) SGS and SGD run in the row direction of the memory cell array, and are commonly connected to the select gate transistors in the NAND cell units in the same rows.
In each NAND cell unit, two neighboring transistors (memory cells and/or select gate transistor) share a single diffusion layer (source or drain)
13
. Also, two neighboring NAND cell units in the column direction share a drain diffusion layer
13
a
or source diffusion layer
13
b.
The select gate transistor on one end side (on the drain diffusion layer
13
a
side) of the NAND cell is connected to a bit line (data line) BLi, and the select gate transistor on the other end side (on the source diffusion layer
13
b
side) to a source line (reference potential line) SL. The source line SL is commonly connected to all the NAND cell units.
As one of data programming methods in the NAND flash EEPROM, a method called self boost programming is known.
When self boost programming is used, since all MOS transistors connected to a given bit line, MOS transistors that construct a column decoder, and the like can be driven by an external power supply potential Vcc or an internal power supply potential Vdd which is generated based on the external power supply potential Vcc and has a value lower than the external power supply potential Vcc, so-called low-voltage operation is allowed. That is, when self boost programming is used, the need for a booster circuit for supplying high potential to these MOS transistors can be obviated, and the total area of peripheral circuits around the memory cell array can be reduced, thus attaining a reduction of the chip area.
The procedures of the data program step based on self boost programming will be explained below.
The data erase step is done to set memory cells in an erase state (“1”-state). After that, data programming is executed in units of pages or bytes.
In the normal program step, in each NAND cell unit, programming is done in units of cells in the order from a memory cell farthest from a bit line (a memory cell on the source line side) toward memory cells on the bit line side. On the other hand, in random programming, programming is done for an arbitrary one of a series circuit of a plurality of memory cells connected between the bit and source lines.
As shown in
FIG. 3
, in self boost programming, a gate electrode (select gate line) SG
2
of select gate transistors S
21
and S
22
on the source line side is set at 0V to set these select gate transistors S
21
and S
22
in a cutoff state.
Next, 0V (data “
0
”) is applied to a bit line (selected bit line) BL
1
to which a memory cell A (M
21
) that is to undergo “0”-programming (“0”-programming memory cell) is connected, and a plus potential (data “1”) is applied to a bit line (unselected bit line) BL
2
to which a memory cell B (M
22
) that is to undergo “1”-programming (“1”-programming memory cell), i.e., a program inhibition cell, is connected. This plus potential is set at a value equal to or higher than a potential applied to a gate electrode (select gate line) SG
1
of select gate transistors S
11
and S
12
on the drain side.
At this time, the select gate transistor S
11
on the drain side is turned on, and the potential (0V) on the bit line BL
1
is transferred to the channel of the memory cell A (M
21
). Also, the select gate transistor S
12
on the drain side is initially turned on, and an initial potential is transferred to the diffusion layer (source/drain) of the memory cell B (M
22
). After that, the select gate transistor S
12
on the drain side is cut off.
Note that the plus potential applied to a bit line BL
2
may be lower than that to be applied to the gate electrode (select gate line) SG
1
of the select gate transistors S
11
and S
12
on the drain side. In this case, it is necessary to cut off the select gate transistor S
12
on the drain side.
In this state, a selected word line (control gate line) WL
2
is set at a program potential Vpp, and unselected word lines (control gate lines) WL
1
and WL
3
to WLN in the selected block are set at a passing potential Vpass (Vpp>Vpass>Vcc) that at least turns on memory cells.
For example, these potentials Vpp and Vpass are applied at the following timings.
The potential of the select gate line SG
1
of the select gate transistors on the bit line side are set at a power supply potential Vcc. When the potentials of all the unselected word lines (control gate lines) are set at a passing potential Vpass, since memory cells M
11
to MN
1
and the select gate transistor S
11
in the NAND cell unit connected to the bit line BL
1
are turned on, the potential (0V) on the bit line BL
1
are transferred to the channels of the memory cells M
11
to MN
1
.
Also, to the channels of memory cells M
12
to MN
2
in the NAND cell unit connected to the bit line BL
2
charges are transferred from the bit line BL
2
via the select gate transistor S
12
. Hence, the channel potentials of the memory cells M
12
to MN
2
in the NAND cell unit connected to the bit line BL
2
gradually rise, and reach an initial potential obtained by subtracting a threshold value Vth of the select gate transistor S
12
from a bit line potential VBL
2
.
When the channel potentials have reached the initial potential, the select gate transistor S
12
is cut off, and the channels of the memory cells M
12
to MN
2
float. At this time, 0V or a plus potential VSL which is high enough to cut off the select gate transistor S
22
on the source side is applied to the source line. When the unselected word lines are set at Vpass, the potentials of the channel and the diffusion layer of the memory cell are boosted.
After that, a program potential pulse Vpp is applied to the selected word line WL
2
.
Hence, the channel potential of the “0”-programming memory cell A (M
21
) is set at 0V, and the potential of the word line (control gate line) WL
2
is set at Vpp, thus executing a “0”-programming operation (an operation for injecting electrons into the floating gate electrode) for the memory cell A (M
21
).
On the other hand, the initial potential of the channel of the “1”-programming memory cell B (M
22
) is VBL
2
−Vth. On the other hand, since the channel of the memory cell B (M
22
) is floating, when the passing potential pulse Vpass is applied to the unselected word line WL
1
, WL
3
−WLN, the channel pote

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