Nonvolatile semiconductor memory

Static information storage and retrieval – Floating gate – Particular connection

Patent

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Details

36518529, 3651853, G11C 1134

Patent

active

056151489

ABSTRACT:
EEPROM for directly outputting addresses of those in which erasing failure occurs among a plurality of blocks to be erased for erasing by a plural block simultaneous erasing system to an outside of a chip and enabling a system side to directly identify the addresses thereof is provided with a plurality of cell blocks each having an array of nonvolatile memory cells, plural block simultaneous erasing control arrangement for performing cell data erasing from a plurality of cell blocks specified as to be erased for simultaneous data erasing and a block address outputting circuit for outputting, when existence of erase failure blocks is detected after block simultaneous erasing, addresses thereof to the outside of the chip.

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