Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

1992-12-28

1996-02-06

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 365201, 36518512, 36518523, G11C 1134

Patent

active

054901073

ABSTRACT:
A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (V.sub.CC), the gate of the transistor being connected to a low source voltage (V.sub.ss) to provide an internal source voltage (V.sub.ci), a combination of an arrangement for dropping the external source voltage (V.sub.cc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (V.sub.pp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (V.sub.ref) as a lower threshold (V.sub.th) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (V.sub.ref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

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