Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

1989-06-06

1991-05-21

Moffitt, James W.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365185, G11C 700, G11C 1606

Patent

active

050181084

ABSTRACT:
A memory cell array includes a matrix array of a plurality of memory cells. These memory cells are non-volatile transistors. The memory cells which are arrayed in each row of the memory array, are coupled with a plurality of word lines. The word lines are selected by a row decoder made up of a plurality of partial decoders. In this case, a constant voltage output circuit, which is provided at the outputs of the partial decoders of the row decoder, outputs a constant voltage lower than a power source voltage to a corresponding word line of those word lines when the corresponding word line is selected by the outputs of the partial decoders.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3457435 (1969-07-01), Burns et al.
patent: 4523301 (1985-06-01), Kadota et al.
patent: 4598390 (1986-07-01), Chan
Sumito Tanaka and Mitsuaki Ishikawa, "One-Dimensional Writing Model of n-Channel Floating Gate Ionization-Injection MOS (FIMOS)", IEEE Transactions on Electron Devices, vol. ED-28; No. 10, Oct. 1981 pp. 1190-1197.

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