Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

Filed on

1989-10-18

Date issued

1991-10-01

Examiner

James, Andrew J.

Other Related Categories

357 6, 357 238, 357 2311, 357 2314, 357 41, 357 45, H01L 2968, H01L 2906, H01L 2978

Type

Patent

Status

active

Patent number

050538411

Description

ABSTRACT:
A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions. Of two cell transistors adjacent to each other in a length direction of the channel region, the source region of one cell transistor is common to the drain region of the other cell transistor, and the cell transistors adjacent to each other in the widthwise direction of the channel region are element-isolated by an element isolation region formed in the semiconductor substrate between the channel regions.

REFERENCES:
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4466081 (1984-08-01), Masuoka
patent: 4531203 (1985-07-01), Masuoka et al.
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4803529 (1989-02-01), Masuoka
patent: 4853895 (1989-08-01), Mitchell et al.

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