Nonvolatile semiconductor memories with a NAND logic cell...

Details Nonvolatile semiconductor memories with a NAND logic cell... Nonvolatile semiconductor memories with a NAND logic cell...

1994-03-14

2003-11-18

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C365S230060

Reexamination Certificate

active

06650567

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to nonvolatile semiconductor memories, and more particularly to nonvolatile semiconductor memories with a NAND logic memory cell structure.
A nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) or MROM (Mask Read Only Memory) has a memory cell structure based on NOR logic or NAND logic. A NAND logic structure requires fewer select transistors per cell and fewer contact holes between bit lines; accordingly, a NAND logic memory cell structure is used in most nonvolatile semiconductor memories. A typical NAND logic memory cell consists of a plurality of unit memory strings each having a memory cell transistor for storing data and string select means for selecting a unit memory string in which a desired memory cell transistor is located. U.S. Pat. No. 4,142,176, issued on Feb. 27, 1979 discloses a nonvolatile semiconductor memory having a cell array wherein string select means and a NAND logic memory cell transistor are serially connected. Specifically, in a plurality of unit memory strings constituting a cell array, a string select transistor for selecting a memory string is serially connected to a plurality of series-connected memory cell transistors for storing data, and a power supply line and a bit line are respectively connected to both ends of the string select transistor and the memory cell transistor. During a data access operation, a voltage is supplied to the bit line, a string operation of the string select transistor results in a selection of and the memory cell transistor on the selected memory string. However, in such a NAND logic memory cell structure, one unit memory string is connected to one bit line. This arrangement is not suitable for high integration of a memory circuit due to the pitch necessarily required between bit lines.
To overcome that disadvantage, an improved structure has been proposed in which two unit memory strings are connected to one bit line, as disclosed in Japanese Patent Provisional Publication No.
2-65170
. Referring to
FIG. 1
, two parallel unit memory strings are connected to a bit line BL selected by a column decoder within a chip. String select transistors MS
10
A, MS
11
A, MS
20
A and MS
21
A selected by a row decoder and n memory cell transistors M
10
A, . . . M
1
nA, M
20
A, . . . M
2
nA driven by word lines WL
0
, . . . , WLn are serially connected to the memory string. Since two string select transistors are connected to one unit memory string, it is possible to independently select two unit memory strings connected to one bit line. During reading and writing operations, only one of two string select transistors is set to logic “high” by an address applied to the chip and simultaneously only one selected word line out of word lines WL
0
, . . , WLn is set to logic “low”. For example, if string select line SS
0
and word line WL
0
are selected by a decoded address, the string select lines SS
0
and SS
1
are respectively set to logic “high” and “low”, and the word line WL
0
is set to logic “low”. All other word lines are set to logic “high”. The string select transistor MS
10
A constituting the memory string is an enhancement transistor having a positive threshold voltage and the string select transistor MS
11
A is a depletion transistor having a negative threshold voltage. The memory cell transistors are either enhancement or depletion transistors according to a programmed state. Therefore, the string select transistors MS
10
A, MS
11
A and MS
20
A are turned on and the string select transistor MS
21
A is turned off. The bit line BL
0
is electrically connected to a connecting point A, and insulated from a connecting point B by the string select transistor MS
21
A. Since it is an enhancement transistor, the memory cell transistor M
1
nA becomes conductive irrespective of the programmed state and connected or disconnected to a ground connecting point C depending on the threshold voltage of the memory cell transistor M
10
A whose gate is connected to the word line WL
0
. If the memory cell transistor M
10
A is a depletion transistor, the bit line BL
0
is electrically connected to the ground connecting point C. If the memory cell transistor M
10
A is an enhancement transistor, the bit line BL
0
is insulated from the ground connecting point C. The voltage of the selected memory cell is typically read out by a sense amplifier (not shown) connected to the bit line.
Referring still to
FIG. 1
, the voltage level of the word lines WL
0
, . . . , WLn is set to logic “high” during a stand-by state. Hence, a gate film of the memory cell transistor may break due to the stress generated by this voltage level, defects in a manufacturing process, or the like. In a very large scale semiconductor integrated circuit including minimally-sized memory cells, this possibility is increased. When defects occur in memory cell transistors, even if the defects are repaired by an error correcting code (ECC) circuit for example, problems such as increased current consumption resulting from the current path formed during the stand-by state from the word line voltage applied to the destroyed gate film to ground.
Another conventional nonvolatile semiconductor memory having a NAND logic cell structure is disclosed in Korean Patent Application No. 1991-6569, filed Apr. 24, 1991. Referring now to
FIG. 2
, switching means MG
1
B, MG
2
B, . . . are controlled by a ground select signal GSS as a decoding signal. By the switching means MG
1
B, MG
2
B, . . . , each memory string is selectively connected to a ground connecting point. That is, the switching means MG
1
B, MG
2
B, . . . repairs the increase of current during the stand-by state of a memory device. Even if a transistor selected by word lines WL
0
, . . . , WLn, bit lines BL
0
, BL
1
, . . , and first and second string select signals SS
0
and SS
1
forms a current path to the ground connecting point during the stand-by state, since switching transistors MG
1
B, MG
2
B, . . . are turned off and on by the ground select signal GSS during the stand-by operation and reading operation, respectively, the increase of the current caused by the breakdown of the gate film of the transistor during the stand-by operation of the chip is prevented. Though not shown in the drawing, the ground select signal GSS is generated by a decoding operation of a row decoder. During a select operation of the memory cell transistor, the ground select signal GSS is logic “high”, and during other operation including the stand-by operation, the ground selected signal GSS is logic “low”.
However, as the packing density of semiconductor integrated circuits increases, the separation between metal bit lines formed on the semiconductor substrate of a chip decreases significantly. Therefore, a bridge phenomenon, or short, caused by a particle during a manufacturing process may frequently occur, and is difficult to repair. In semiconductor memories 64 Mbits (mega: 10
6
) or 128 Mbits in size, the bit line is generally formed with metal, and the bridge phenomenon is a great obstacle in the manufacturing process.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a reliable nonvolatile semiconductor memory suitable for increased chip packing density.
It is another object of the present invention to provide a low power consumption nonvolatile semiconductor memory suitable for high integration.
It is yet another object of the present invention to provide a nonvolatile semiconductor memory which prevents a bridge phenomenon between metals in a high integration chip.
It is still another object of the present invention to provide a nonvolatile semiconductor memory with a NAND cell array structure which prevents unnecessary current consumption during a stand-by operation.
It is still yet another object of the present invention to provide a nonvolatile semiconductor memory with a NAND cell array structure for facilitating design.
It is a further object of the present invention to provide a nonvolatil

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