Nonvolatile reprogrammable interconnect cell with programmable b

Details Nonvolatile reprogrammable interconnect cell with programmable b Nonvolatile reprogrammable interconnect cell with programmable b

1998-12-04

2000-10-24

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518514, 257321, G11C 1604

Patent

active

061377287

ABSTRACT:
Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.

REFERENCES:
patent: 5761120 (1998-06-01), Peng et al.
patent: 5838040 (1998-11-01), Salter et al.

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