Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-06-20
2003-11-25
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170, C365S185180
Reexamination Certificate
active
06654281
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for programming it and, in particular, to a flash EEPROM memory with a novel NOR gate transistor array architecture.
The majority of computer units or computers currently use magnetic disk drives for storing relatively large volumes of data. However, such disk drives or mechanical storage devices require a relatively large space and have a multiplicity of moving parts. Consequently, they are prone to faults and have a considerable current consumption. Furthermore, future computer units or computers and other digital devices such as, for example, digital cameras or palm devices or personal telecommunication/telephone apparatus (PTAs) will become smaller and smaller, for which reason conventional mechanical storage devices are unsuitable.
As an alternative to such conventional mechanical storage devices nonvolatile semiconductor memory devices have recently gained increasing acceptance, these devices being known for example as flash memory EEPROM, EPROM and the like. The so-called NAND and NOR semiconductor memory devices are known as the most important representatives of such electrically erasable and electrically programmable memory devices. In both semiconductor memory devices the memory cells have so-called one-transistor memory cells, a drain region and a source region usually being formed in a semiconductor substrate and there being situated above the channel section lying in between an insulated charge-storing layer and, disposed above the latter, an insulated control layer. To program such a one-transistor cell, relatively high voltages are applied to the control layer and the drain region, while the source region is usually grounded. Under such circumstances charge carriers are introduced into the charge-storing layer by channel injection, injection of hot charge carriers and/or Fowler-Nordheim tunneling. In this case, the charge carriers remain in the charge-storing layer and effect a lasting change in the switching behavior of the respective field-effect transistor.
Whereas in the NAND semiconductor memory devices described above a multiplicity of one-transistor memory cells are serially connected to one another and are driven via a common selection gate, the respective one-transistor memory cells in NOR semiconductor memory devices are organized in parallel or in matrix form, as a result of which each memory cell can be selected individually.
The present invention relates exclusively to such NOR semiconductor memory devices.
In accordance with known nonvolatile NOR semiconductor memory devices, a multiplicity of one-transistor memory cells are disposed in a matrix form, i.e. in rows and columns. As has already been described above, each one-transistor memory cell contains mutually spaced-apart drain and source regions, which are formed in a semiconductor substrate. In this case, a control layer is respectively connected row by row to an associated word line. In contrast, the drain regions of the respective one-transistor memory cells are connected column by column to a respective bit line. The source regions of the nonvolatile NOR semiconductor memory device are all grounded or are all connected to one another, which is why such a NOR semiconductor memory device is referred to as a memory device with a “common source” architecture.
The relatively high current consumption during a programming operation is disadvantageous, however, in the case of such conventional semiconductor memory devices. This is because the current consumption is essentially determined from the sum of a programming current of the selected memory cells (i.e. memory cells to be programmed) and of a leakage current of non-selected memory cells. Although, for each individual memory cell, the leakage current of the non-selected memory cells lies far below a respective leakage or programming current of a selected memory cell, the sum of the leakage currents of all the unselected memory cells is of a similar order of magnitude to the programming current for the selected memory cell, particularly in the case of large arrays or memory cell arrays.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a nonvolatile NOR semiconductor memory device and a method for programming the memory device that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which a leakage current in the non-selected memory cells and thus a total current consumption are reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a nonvolatile NOR semiconductor memory device containing a semiconductor substrate and a multiplicity of one-transistor memory cells formed in the semiconductor substrate and disposed in a matrix form. The one-transistor memory cells has mutually spaced-apart drain regions and source regions, a first insulating layer, a charge-storing layer, a second insulating layer, and a control layer. A multiplicity of word lines are connected to and row-by-row drive the one-transistor memory cells, and the word lines are substantially formed by the control layer. A multiplicity of bit lines are connected to and column-by-column drive the one-transistor memory cells. The bit lines each have a source line and a drain line for enabling a selective driving of the drain regions and the source regions in respective columns of the one-transistor memory cells. The source line and the drain line are formed in a meandering shape, a zigzag shape or an undulating form.
In particular the use of selectively drivable source lines and drain lines for respective bit lines enables selective driving of the respective source regions, as a result of which the current consumption during programming or the occurrence of leakage currents can be significantly reduced.
The respective source and drain lines are preferably formed in meandering, zigzag or undulating form, thereby producing a significant saving of area and enabling large scale integrated semiconductor memory devices.
The space requirement is reduced further by forming the source and drain lines in different electrically conductive layers.
In accordance with an added feature of the invention, a common electrically conductive layer is provided and the source line and the drain line are formed from the common electrically conductive layer. The source line and the drain line are disposed substantially parallel to one another.
Alternatively, the source line and the drain line are disposed substantially in an overlapping manner in different electrical conductive layers.
In accordance with an additional feature of the invention, drain/source contacts are disposed substantially rectilinearly for producing a connection between the drain and source lines and the drain and source regions of the one-transistor memory cells.
In accordance with a further feature of the invention, a metallization layer is provided and the source line and the drain line are formed from the metallization layer.
In accordance with another feature of the invention, a plurality of metallization layers are provided and the source line and the drain line are formed in the plurality of metallization layers.
In the method for programming the nonvolatile NOR semiconductor memory device, preferably predetermined voltages are applied both to the source line and to the drain line. As an alternative to this, however, the programming voltages can also be applied only to the drain lines or source lines, while their associated source lines or drain lines are floating or have a floating voltage.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for programming a memory cell. The method includes providing a nonvolatile NOR semiconductor memory device; applying a predetermined gate voltage to a selected one of the word lines; applying a predetermined source voltage to a selected source line; and applying a predeter
Georgakos Georg
Huckels Kai
Kriz Jakob
Kutter Christoph
Liebelt Andreas
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Phan Trong
Stemer Werner H.
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