Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-02-09
2002-09-24
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185130, C365S185190
Reexamination Certificate
active
06456527
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a nonvolatile multilevel memory and a reading method therefor, in particular for flash memories.
BACKGROUND OF THE INVENTION
As known, the need for nonvolatile memories with an always increasing density, is leading to design of multilevel memories, wherein data, stored in the floating gate regions of the cells, is coded on several logic levels, by dividing the quantity of charge stored in each cell.
FIG. 1
shows the characteristic linking the gate-source voltage V
gs
with the drain-source current I
ds
of a flash cell, biased in known manner with reading voltages, for a two-level memory, i.e., a memory wherein data is coded in each memory cell by a bit having two possible values, associated respectively with an off and an on condition of the cell, in turn dependent on whether the cell has been programmed. In particular, in
FIG. 1
, V
tv
and V
tw
represent the value of the gate-source voltage V
gs
at which a flash cell begins to conduct current, respectively for a virgin (erased) cell, and a written cell. In a memory of this type, the logic value “1” is generally associated to the characteristic having the threshold voltage V
tv
, generally comprised between 0.5 and 2.5 V, and the logic value “0” is generally associated to the characteristic having the threshold voltage V
tw
, and is generally greater than 5 V.
It is also known that reading a memory cell is based on converting the current flowing in the memory cell, at a specific gate-source voltage V
gs
, into a voltage then translated to a CMOS level, at the output of a comparator circuit. An example of a known reading circuit is shown in
FIG. 2
; the reading circuit
1
comprises a current/voltage converter (comprising a current mirror circuit
2
), and a comparator
3
; the current mirror circuit
2
has two nodes, connected respectively to a memory cell
4
and to a reference cell
5
, as well as to the inputs of the comparator
3
, the output whereof supplies the signal at CMOS level, thus coding the read bit.
For multilevel cells, the plane (V
gs
, I
ds
) is divided by several characteristics, as shown for example in
FIG. 3
, concerning the storage of two bits per cell, corresponding to four logic values 11, 10, 01 and 00. In this case, the four logic values correspond to four different threshold values Vt
1
, Vt
2
, Vt
3
and Vt
4
, which in turn are associated with different quantities of charges stored in the floating gate region of the memory cells.
Programming of the cells is affected by uncertainty, and the characteristics both of FIG.
1
and
FIG. 3
represent the central value of the actually obtainable distributions; in fact, to each threshold value a respective distribution of values is associated, comprised between a minimum value and a maximum value, and spaced from the maximum values of the preceding distribution, and/or from the minimum value of the successive distribution, to allow correct reading of the cells. In addition, each distribution can have a different amplitude, as shown for example in
FIG. 4
, showing the distributions associated with memory cells storing each two bits, using a not uniform scale.
Also here, reading comprises converting the current flowing in the cell, into a voltage; the voltage thus obtained is then compared with different intermediate voltage values within the above-described threshold distributions.
One of the problems arising when reading multilevel cells, is caused by the reading voltage applied to the gate terminals of the cells to be read; in fact, at the reading voltage, all the read cells (optionally except the cells programmed to the highest threshold value) must be on, to compare the converted voltage with the various voltage levels; consequently, the reading voltage must be at least greater than the last but one threshold value (V
t3
in
FIG. 2
; V
R
in
FIG. 4
, here of 6V).
FIG. 5
shows the characteristics variability intervals taking into account the distributions of the threshold voltages shown in
FIG. 4
, as well as three reference current values, I
R1
, I
R2
, I
R3
, (indirectly) compared with the current flowing in the memory cells, at the reading voltage V
R
. In practice, the three reference current values are intermediate between the different distributions of characteristics.
FIG. 6
shows an example of a reading logic circuit
10
, supplying at the output two bits
01
,
02
stored in a cell, after comparison with three reference voltages V
1
, V
2
, V
3
, corresponding to the reference current values I
R1
, l
R2
, I
R3
of FIG.
5
.
In detail, the reading logic circuit
10
comprises three comparators
11
,
12
,
13
, receiving at their non-inverting inputs a voltage V
m
, obtained from the conversion of the current flowing in a read memory cell and receiving at their inverting input a respective reference voltage V
1
, V
2
, V
3
. The output of the comparator
11
is connected to a first input of a first, three-input AND gate
14
; the output of the comparator
12
defines a first output
15
of the reading logic circuit
10
, and is connected to a second input of the first AND gate
14
, via a first inverter
16
; the output of the comparator
13
is connected to a third input of the first AND gate
14
, and to an input of a second, two-input AND gate
17
. The output of the first AND gate
14
is connected to a second input of the second AND gate
17
, via a second inverter
18
. Thereby, the output
15
of the reading logic circuit
10
supplies the first bit
01
; the output of the second AND gate
17
defines a second output
19
of the reading logic circuit
10
, and supplies the second bit
02
.
The memory cells of the considered type have small gain (20&mgr;A/V); in addition, the present architectures require that the reading voltage V
R
(at least equal to the lower limit of the threshold voltage distribution that is furthest to the right in
FIG. 5
, as previously explained), should not be too high. These conditions are a problem when reading cells storing four levels (two bits); in fact, it is necessary to distinguish currents differing from one another by 10 &mgr;A, but have different common mode contributions, since the difference between the different currents is always 10 &mgr;A, but the absolute value varies between 0 and 70 &mgr;A. The distinction is also made more complex by the gain variations associated with the various threshold voltages.
In known circuits, used for reading cells storing one or two bits, the current/voltage converter connected to the cell, and the comparators connected with the converter, are optimized on the basis of the present current and voltages. However, this solution is difficult to implement for cells storing more than four levels, in particular when a cell access time (overall reading time) is to be ensured of approximately 100-200 ns, as in the present circuits.
FIG. 7
refers to the storage of three bits per cell, corresponding to eight different threshold voltages (eight different binary words), and shows the threshold voltage variability intervals for the various binary words, ignoring the spacing necessary to avoid reading uncertainties.
FIG. 7
also shows a possible distribution of the characteristics for the binary word
101
.
Instead of using a constant value reading voltage, reading may be effected here by increasing the voltage applied to the gate terminal of the cell to be read from the upper distribution limit of the lower threshold voltage (for example 2 V in FIG.
7
), to the lower distribution limit of the higher threshold voltage (6 V in FIG.
7
). The reading voltage V
R
can be increased according to a continuous or discrete ramp; in the latter case (FIG.
8
), the number of steps of the voltage ramp can be equivalent to the number of programmable threshold voltage levels, less one (seven, in this case).
In particular, the memory cell can be read using a reading circuit
23
shown in
FIG. 9
; in detail, the reading circuit
23
comprises a voltage/current converter
24
, comprising two diode-connected PMOS transistors
25
Campardo Giovanni
Micheloni Rino
Iannucci Robert
Jorgenson Lisa K.
Le Vu A.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
LandOfFree
Nonvolatile multilevel memory and reading method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile multilevel memory and reading method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile multilevel memory and reading method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2840988