Nonvolatile memory with index programming and reduced verify

Details Nonvolatile memory with index programming and reduced verify Nonvolatile memory with index programming and reduced verify

2008-06-12

2010-11-02

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185240, C365S185330, C365S189040, C365S189110

Reexamination Certificate

active

07826271

ABSTRACT:
In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.

REFERENCES:
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5289401 (1994-02-01), Shima
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5701266 (1997-12-01), Fazio et al.
patent: 5729489 (1998-03-01), Fazio et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6366496 (2002-04-01), Torelli et al.
patent: 6614683 (2003-09-01), Parker
patent: 6714448 (2004-03-01), Manea
patent: 7042766 (2006-05-01), Wang et al.
patent: 7095654 (2006-08-01), Quader et al.
patent: 7151692 (2006-12-01), Wu
patent: 7158413 (2007-01-01), Kasai et al.
patent: 7366014 (2008-04-01), Micheloni et al.
patent: 7414887 (2008-08-01), Guterman et al.
patent: 7447081 (2008-11-01), Cahn
patent: 7453731 (2008-11-01), Tu et al.
patent: 7508713 (2009-03-01), Sekar et al.
patent: 7508715 (2009-03-01), Lee
patent: 7545677 (2009-06-01), Lee et al.
patent: 7551483 (2009-06-01), Cernea
patent: 7590007 (2009-09-01), Futatsuyama
patent: 7606084 (2009-10-01), Kamei
patent: 7643348 (2010-01-01), Cernea
patent: 2002/0191444 (2002-12-01), Gregori et al.
patent: 2003/0002374 (2003-01-01), Tedrow
patent: 2005/0219906 (2005-10-01), Wu
patent: 2006/0140007 (2006-06-01), Cernea et al.
patent: 2007/0030732 (2007-02-01), Micheloni et al.
patent: 2007/0091681 (2007-04-01), Gongwer et al.
patent: 2007/0159891 (2007-07-01), Tu et al.
patent: 2007/0263450 (2007-11-01), Cernea et al.
patent: 2008/0062765 (2008-03-01), Tu et al.
patent: 2008/0253193 (2008-10-01), Cernea
patent: 2008/0253197 (2008-10-01), Cernea
patent: 2008/0310234 (2008-12-01), Lee et al.
patent: 2009/0310418 (2009-12-01), Cernea
patent: 2009/0310420 (2009-12-01), Cernea
patent: 2009/0310421 (2009-12-01), Cernea
patent: 0 913 832 (1999-05-01), None
patent: WO 2008/002832 (2008-01-01), None
patent: WO 2008/002832 (2008-01-01), None
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2009/044554, mailed on Jul. 30, 2009, 12 pages.
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 12/138,371 on Jan. 13, 2010, 19 pages.
USPTO, “Notice of Allowance and Fee(s) Due,” mailed in related U.S. Appl. No. 12/138,371 on May 13, 2010, 18 pages.

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