Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-12-05
2002-11-19
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185210
Reexamination Certificate
active
06483748
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and particularly, to a nonvolatile semiconductor memory device capable of operating in the background operation mode in which a data is externally read out in an erasure/programming operation in the interior thereof.
2. Description of the Background Art
FIG. 17
is a block diagram schematically showing a configuration of a conventional nonvolatile semiconductor memory device. In
FIG. 17
, the conventional nonvolatile semiconductor memory device includes a plurality of banks B#
1
to B#
4
. Each of the banks B#
1
to B#
4
includes: a memory array MA having a plurality of nonvolatile memory cells arranged in rows and columns; a predecoder PD for predecoding a supplied address signal; a row decoder RD for decoding a row predecode signal supplied from the predecoder PD to select an addressed row of the memory array MA; a column decoder CD for decoding a column predecode signal supplied from the predecoder PD to generate a column select signal selecting an addressed column of the memory array MA; and a Y gate YG for selecting a corresponding column of the memory array MA according to the column select signal supplied from the column decoder CD. The banks B#
1
to B#
4
can be addressed independently and individually.
The nonvolatile semiconductor memory device further includes: an address buffer
1
taking in an address signal AD supplied externally therein according to a control signal CTL and generating an internal address signal to supply it to the banks B#
1
to B#
4
; a data buffer
2
for inputting and outputting a data between the data buffer
2
and an external device; a write data buffer
4
receiving an internal write data from the data buffer
2
to store the data therein; write circuit and sense amplifier blocks
5
a
to
5
d
, provided corresponding to the respective banks B#
1
to B#
4
, each transmitting a write data to a selected memory cell of a corresponding bank and reading a data from a selected memory cell of a corresponding bank; a bank pointer
3
for activating a bank specified by a bank address signal supplied from the address buffer
1
; an erasure/programming verification circuit
6
receiving a verify data read out from the write circuit and sense amplifier blocks
5
a
to
5
d
and a write data stored in the write data buffer
4
in a write operation, and for verifying whether or not, in a selected bank, erasing has been correctly performed and whether or not, in a selected bank, data programming has been correctly performed; and internal control circuit
7
receiving a control signal CTL supplied externally, a command CMD specifying an operating mode supplied externally and a bank address signal supplied from the bank pointer
3
, and controlling operations of the data buffer
2
and the bank pointer
3
but as well as setting an internal address signal generated from the address buffer
1
in an internal operation.
The control signal includes a chip enable signal /CE, a write enable signal /WE and an output enable signal /OE. The command CMD specifies a data erase mode, a data write mode and the like, and is supplied through a data bus.
The nonvolatile semiconductor memory device shown in
FIG. 17
is a flash memory in which one memory cell is formed of one floating gate field effect transistor. Data storage in a memory cell is achieved by injection/extraction of electric charges to/from the floating gate of a floating gate field effect transistor to change a threshold voltage thereof.
It has been established that an access time for a data read operation ranges from 50 nsec (nanoseconds) to 200 nsec and on the other hand, an erasure/programming operation requires to change a threshold voltage of a memory cell transistor (in a unit of a memory block) and therefore, it takes a relatively long time ranging from 2 &mgr;s (microseconds) to 5 s (seconds). In the prior art, it is impossible to read out a data in the chip during an internal operation in which the erasure/programming operation is performed. In a case where a plurality of banks B#
1
to B#
4
are provided as shown in
FIG. 17
, however, while an internal operation for programming/erasing is performed on a bank, can be accessed for data reading from another bank. An operation in which while an internal operation is actually performed in one bank, a data can be read out from another bank, is called a BGO (background operation) function. In order to realize this BGO function, an external operation address signal and an internal operation address signal are generated from the address buffer and further, the write circuit and sense amplifier blocks
5
a
to
5
d
are provided corresponding to the respective banks B#
1
to B#
4
. According to an operating mode, the write circuit and sense amplifier blocks
5
a
to
5
d
are coupled to either the erasure/programming verification circuit
6
or the data buffer
2
. The selective connection is performed under control of the internal control circuit
7
according to a bank specifying signal supplied from the bank pointer
3
.
FIG. 18
is a circuit diagram representing a construction of a sense amplifier included in each of the write circuit and sense amplifier blocks
5
a
to
5
d
shown FIG.
17
. In
FIG. 18
, the sense amplifier includes: a current sense circuit
901
, activated when a sense amplifier enable signal ZSE is activated, for amplifying a data transmitted through an internal data transmission line
900
from the Y gate YG; an N channel MOS transistor
902
, made conductive when the sense amplifier enable signal ZSE is deactivated, for precharging a node
907
to the ground voltage level; two cascaded CMOS inverters
903
and
904
amplifying a signal on the node
907
; an internal output circuit
905
, activated when an external read output enable signal EXRDE is activated, for buffering (amplifying) a signal supplied from the CMOS inverter
904
to transmit the buffered signal to the data buffer
2
; and an internal output circuit
906
, activated when a verify output enable signal VFRDE is activated, for buffering (amplifying) an output signal of the CMOS inverter
904
to supply the output signal to the erasure/programming verification circuit
6
.
The current sense circuit
901
includes: a P channel MOS transistor PQ
1
, made conductive when the sense amplifier enable signal ZSE is activated, for supplying a current to the node
907
; a P channel MOS transistor PQ
2
made conductive when the sense amplifier enable signal ZSE is activated and transmitting a power supply voltage when made conductive; an N channel MOS transistor NQ
3
connected between the MOS transistor PQ
2
and the ground node, and receiving the sense amplifier enable signal ZSE at a gate thereof; an N channel MOS transistor NQ
1
connected between the node
907
and the internal data line
900
, and coupled with drains of the MOS transistors PQ
2
and PQ
3
at a gate thereof; and an N channel MOS transistor NQ
2
connected in parallel to the MOS transistor NQ
3
, and connected to the internal data transmission line
900
at a gate thereof.
The first internal output circuit
905
includes: P channel MOS transistors PQ
3
and PQ
4
connected serially between a power supply node and a first output node; and N channel MOS transistors NQ
4
and NQ
5
connected serially between the first output node and a ground node. An output signal of the CMOS inverter
904
is supplied to the gates of the MOS transistors PQ
3
and NQ
5
, and the external read output enable signal EXRDE is supplied to the gate of the MOS transistor PQ
4
through an inverter. Further, the external read output enable signal EXRDE is supplied to the gate of the MOS transistor NQ
4
.
The second internal output circuit
906
includes: P channel MOS transistors PQ
5
and PQ
6
connected serially between a power supply node and a second output node; and N channel MOS transistors NQ
6
and NQ
7
connected serially between the
Futatsuya Tomoshi
Miyawaki Yoshikazu
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