Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2011-03-29
2011-03-29
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C365S185230
Reexamination Certificate
active
07915092
ABSTRACT:
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
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Hsu Fu-Chang
Lee Peter W.
Ma Han-Rei
Tsao Hsing-Ya
Wu Koucheng
Abedneja Assets AG L.L.C.
Le Thao P.
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