Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-12-21
2003-03-18
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170, C365S185330, C365S052000
Reexamination Certificate
active
06535422
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory system, and more particularly to a technique effectively applied to a flash memory system that has electrically erasable and programmable flash memories.
Flash memories are nonvolatile semiconductor memories that can store information by injection and ejection of electrons to and from floating gates. The flash memories have a memory cell transistor comprising a floating gate, control gate, source, and drain. The memory cell transistor rises in threshold voltage when electrons are injected to the floating gate, and falls in threshold voltage when electrons are ejected from the floating gate. The memory cell transistor stores information according to a rise or fall in threshold voltage to a word line voltage (control gate applied voltage) for data reading. Although not specially limited, in this specification, a low threshold voltage state of a memory transistor is referred to as erasure state, and a high threshold voltage state thereof is referred to as write state.
Memory modules in which plural such flash memories are provided and a data bus and address bus are used in common include an IC memory disclosed in Japanese Published Unexamined Patent Application No. Hei 11(1999)-273370. In the IC memory, a data control unit inputs and outputs commands and various data between a data bus and memory chips, and a command control unit generates chip enable for a memory chip from a chip enable signal inputted from the outside according to a command from the outside, generates and outputs an internal serial clock signal for the memory chip by a serial clock generator, and performs reading, writing, or erasure of contiguous data for an identical sector address of a memory chip by one input of a command and the sector address.
SUMMARY OF THE INVENTION
Memory systems employing nonvolatile memories such as flash memories have a fixed number of memory chips mounted therein, and are manufactured by storage capacity such as, e.g., 64 MB and 128 MB products. In a user system, a memory system having a necessary storage capacity is mounted according to the configuration of the user system.
However, in the case where memory systems are manufactured for each storage capacity by directly mounting plural nonvolatile memory chips on one board, since the storage capacity of the memory systems cannot be changed, manufacturers may have an excessive stock for each storage capacity. If an error exists in one of plural memory chips mounted on a board in a memory system, the memory system containing such a chip is treated as a defective product.
Further, in the case where a memory system used in place of hard disk is applied, it is desired that the memory system has a large storage capacity. In that case, the inventor examined memory systems in which a large number of memory chips are mounted, and found that, if plural nonvolatile memories mounted on one board were reset at a time, a large current might flow instantaneously due to the reset, a reset period might be prolonged because of a decrease in a supply voltage of a power circuit, reset processing might not be performed adequately, and the power circuit might be damaged.
An object of the present invention is to provide a nonvolatile memory system whose storage capacity can be easily changed.
Another object of the present invention is to provide a technique for relaxing a large current caused by a reset operation on nonvolatile memories.
These and other objects, and novel features of the present invention will become apparent from the following description and the accompanying drawings.
A brief description will be made of typical inventions disclosed in this application.
That is, a nonvolatile memory system of the present invention comprises: plural memory modules each including plural nonvolatile memories; a controller for controlling the operation of the plural memory modules according to access requests from the outside; and a module selecting decoder that obtains a module enable signal for selectively enabling the memory modules by decoding a selection signal outputted from the controller, wherein the memory modules can be freely mounted or dismounted.
According to the above described means, the module selecting decoder forms a module enable signal for selectively enabling the above described memory modules by decoding a selection signal outputted from the controller. A memory module is selected by the module enable signal. Since the memory modules can be freely mounted or dismounted, the storage capacity of an overall nonvolatile memory system can be changed by increasing or decreasing the memory modules.
At this time, the above described plural memory modules each can be easily configured so as to include a chip selecting decoder for selecting the nonvolatile memories by decoding a selection signal outputted from the controller, and a first control logic that forms a chip selection signal for selecting the nonvolatile memories, based on an output signal of the module selecting decoder and an output signal of the chip selecting decoder.
The above described plural memory modules each can be easily configured so as to include: a chip selecting decoder for selecting the above described nonvolatile memories by decoding a selection signal outputted from the controller; a first control logic that form a chip selection signal for selecting the above described nonvolatile memories, based on an output signal of the module selecting decoder and an output signal of the above described chip selecting decoder; and a second control logic for arresting transmission of control signals from the controller to the plural nonvolatile memories in memory modules not selected by an output signal of the module selecting decoder.
As described above, since control signals outputted from the controller are not transmitted to the plural nonvolatile memories in memory modules not selected by the output signal of the module selecting decoder, even if the number of memory modules is increased, it can be prevented that loads on an output unit of the controller increase to an undesirable level. Therefore, even if the number of memory modules is increased to achieve a large capacity, the driving capacity of the output unit of the controller does not need to be increased, so that the controller does not need to be redesigned.
A reset control unit can be provided which can reset the plural memory modules at a different timing for each of the memory modules in accordance with indications from the controller. According to the reset control unit, since the memory modules are successively reset at a different timing for each of them, current caused by the resets is dispersed over time, with the result that current caused by the resets of the memory modules can be prevented from concentrating.
A reset control unit can be provided which can reset the plural memory modules at a different timing for each of the plural nonvolatile memories in accordance with indications from the controller. Also in that case, since the memory modules are successively reset at a different timing for each of the nonvolatile memories, current caused by the resets is dispersed over time, with the result that current caused by the resets of the nonvolatile memories can be prevented from concentrating.
The reset control unit can be easily formed by providing information holding means having an output terminal corresponding to an input terminal for a reset signal to each of the memory modules. In this case, the reset signals are successively negated by the controller updating information held in the information holding means. At this time, the information holding means can be easily formed by flip-flop circuit and shift registers.
When having plural nonvolatile memories, the controller can be configured so as to include a memory control unit that enables write interleave in a manner that, concurrently with write operations to part of the plural nonvolatile memories, transfers write data to other nonvolatile memories, and a micro proces
Goto Hiroyuki
Nakamura Yasuhiro
Shibuya Hirofumi
Shiota Shigemasa
Tamura Takayuki
LandOfFree
Nonvolatile memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3015573