Nonvolatile memory structures and access methods

Details Nonvolatile memory structures and access methods Nonvolatile memory structures and access methods

2002-10-09

2004-01-06

Tran, M. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180

Reexamination Certificate

active

06674669

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to nonvolatile memories.
FIG. 1
shows a cross section of a flash memory cell
110
disclosed in U.S. Pat. No. 6,134,144 issued Oct. 17, 2000 to Lin et al. Floating gate
120
, control gate
130
, and select gate
140
are formed over semiconductor substrate
150
. Drain
160
and source
170
are N type doped regions formed in substrate
150
adjacent to select gate
140
and floating gate
120
respectively. P type doped channel region
180
extends in substrate
150
between source
170
and drain
160
. The gates
120
,
130
,
140
are insulated from each other and the substrate by insulating layers.
The cell is programmed by hot electron injection as the control gate
130
is held at a super high voltage of 12 V, select gate
140
is held at 1 V, drain
160
is held at 0 V, and source
170
is held at 5 to 8 V. Hot electrons are injected from channel
180
into floating gate
120
to negatively charge the floating gate.
The cell is erased by Fowler-Nordheim tunneling of electrons from floating gate
120
to source
170
as source
170
is held at 12 V and control gate
130
, drain
160
, and select gate
140
are at 0 V.
FIG. 2
is a circuit diagram of a flash memory array formed with the cells of FIG.
1
. Each cell
110
is shown schematically as an NMOS transistor and a floating gate transistor connected in series. In each row of the array, the select gates
140
are provided by a polysilicon wordline. The wordlines of rows
0
,
1
, etc. are shown respectively as WL
0
, WL
1
, etc., and are also referenced as
140
. In each row, control gates
130
are also provided by a polysilicon line (“control gate line”). The control gate lines of rows
0
,
1
, etc. are shown as CGL
0
, CGL
1
, etc., and are also referenced as
130
. Each control gate line CGLi (i=0, 1, . . . ) is in the same row “i” as wordline WLi.
In each row, source regions
170
are formed as a diffusion line (“source line”) in substrate
150
. Every two adjacent rows share a source line. Thus, rows
0
and
1
share source line SL
0
-
1
, rows
2
and
3
share source line SL
2
-
3
, and so on.
Metal bitlines BL
0
, . . . BL
63
, also referenced as
210
, are perpendicular to the wordlines, the control gate lines, and the source lines. Each bitline is connected to drains
160
of a column of the memory cells.
Decoders (not shown) are positioned on the sides of the array to supply appropriate signals to the wordlines, the control gate lines and the source lines. Additional circuitry (not shown) supplies appropriate signals to the bitlines for the erase and program operations, and connects the bitlines to sense amplifiers (not shown) during the read operations.
The memory array is organized as a number of pages. A page contains eight rows whose source lines
170
are connected together. For example, the source lines SL
0
-
1
, SL
2
-
3
, SL
4
-
5
, SL
6
-
7
of rows
0
-
7
are connected together. The eight control gate lines
130
of each page are also connected together. The individual rows are selected by activating the associated wordlines.
SUMMARY
Connecting together the control gate lines
130
of each page reduces the size of the decoding circuitry needed to select a control gate line. However, the memory cells become more vulnerable to punch-through during programming. Suppose for example that cell
110
.
0
in row
0
, column
0
is being programmed. Control gate line CGL
0
is at 12 V, wordline WL
0
is at 1 V, source line SL
0
-
1
is at 5 to 8 V, and bitline BL
0
is at 0 V. Word lines WL
1
, WL
2
, etc. are at 0 V. During programming, the unselected cell
110
.
1
has the following voltages on its terminals: its control gate
130
is at 12 V, source
170
at 5 to 8 V, drain
160
at 0 V, and select gate
140
at 0 V. Consequently, the voltage on source
170
is passed along channel portion
180
.
1
underlying the floating gate, and a 5 to 8 V potential difference appears across channel portion
180
.
2
underlying select gate
140
. As a result, the cell may experience a high leakage current. In addition, the cell may suffer a punch-through, with a high current flowing from the drain to the source. To reduce the probability of a punch-through, one can increase the length of select gate
140
, but this undesirably increases the cell size. One can also increase the doping level of channel
180
, but this undesirably reduces the cell current when the cell is selected for reading or programming.
The punch-through problem is particularly dangerous for the memory cells in which the select gate is formed as a sidewall spacer because the length of the select gate can be less than one feature size (a feature size is a minimum line width obtainable with the photolithographic processes used in the memory fabrication). Two such cells sharing a source line
170
are shown in FIG.
3
. The cells are manufactured as described in U.S. Pat. No. 6,355,524 issued Mar. 12, 2002 to H. T. Tuan et al., entitled “Nonvolatile Memories and Methods of Fabrication”, incorporated herein by reference. Briefly, insulating layer
310
is formed on a P-doped region of monocrystalline silicon substrate
150
. Doped polysilicon layer
120
is formed on insulator
310
. Then polysilicon
120
(the floating gate layer) is removed between different columns of the array so that the floating gates of different columns would not be connected to each other. The floating gates within each column remain connected to each other at this stage.
Insulator
320
is formed on layer
120
. Doped polysilicon
130
is formed on insulator
320
. Silicon nitride
330
is formed on polysilicon
130
. Then layers
330
,
130
,
320
,
120
,
310
are etched to form stacks
334
extending along each row of the array. In each stack, polysilicon
130
provides a control gate line. Polysilicon
120
is removed between the rows during this etch, so the floating gates
120
become fully isolated from each other.
Insulator
340
is formed on the sidewalls of each stack
334
. (Layer
340
may include thermally grown silicon dioxide and may also include silicon nitride spacers formed by conformal deposition and a maskless etch of silicon nitride.) Silicon dioxide
350
is grown on the exposed portions of substrate
150
.
Conformal polysilicon layer
140
is deposited and etched anisotropically to form spacers on the sidewalls of each stack
334
. The etch does not require a mask over the memory array. Then a masked etch of polysilicon
140
removes the spacers on the source line side of each stack. The spacer on the drain side of the stack provides a wordlines WLi for the corresponding row. Source lines
170
and drain regions
160
are doped at suitable steps during fabrication.
The memory cells of
FIG. 3
can be individually programmed by hot electron injection from channel region
180
to the floating gate. The cells connected to the same source line
170
(a “sector”) can be erased together by Fowler-Nordheim tunneling from the floating gates
120
to the source line
170
or substrate
150
. In one embodiment, the following voltages can be used for the memory operation:
TABLE 1
Sector erase
through source
Sector erase
Program
line
through substrate
Read
Control gate 130
+10 V/0 V
−10 V
−10 V
1.8 V
Drain 160
   0 V/V3**
V4***
Float
1.5
(VCC = 1.8 V)
(VCC = 1.8 V)
Source line 170
   6 V
   5 V
Float
  0 V
Select gate 140
VTN + &Dgr;V1*
0 V
0 V
VCC + &Dgr;V2*
(VCC = 1.8 V)
Substrate 150
   0 V
   0 V
   6 V
  0 V
Notes to Table 1:
*In some embodiments, VTN = 0.6 V, &Dgr;V1 = 0.9 V, &Dgr;V2 = 1.4 V.
**V3 is a voltage above &Dgr;V1.
***V4 is some voltage such that 0 < V4 < VCC.
Slashes are used in Table I to indicate the voltages for selected
on-selected memory rows or columns. For example, in the “Program” column of Table 1, in the row “Drain
160
”, the entry “0 V/V3” indicat

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