Nonvolatile memory having transistor redundancy

Static information storage and retrieval – Floating gate – Particular connection

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365200, 36518533, G11C 700

Patent

active

057485275

ABSTRACT:
A flash memory array comprises a primary row line and a redundant row line each having memory cells therealong. A method of accessing the flash memory array comprises preprogramming all said memory cells. Next, all memory cells are erased simultaneously. Subsequently, all memory cells along the primary row line are programmed and the cells along the redundant row line are selectively programmed. The primary row line is bypassed during any read cycle.

REFERENCES:
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patent: 5157628 (1992-10-01), Tani
patent: 5220518 (1993-06-01), Haq
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5329488 (1994-07-01), Hashimoto
patent: 5388076 (1995-02-01), Ihara

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