Nonvolatile memory having a trap layer

Details Nonvolatile memory having a trap layer Nonvolatile memory having a trap layer

2005-08-23

2005-08-23

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C365S185030

Reexamination Certificate

active

06934194

ABSTRACT:
A nonvolatile memory has a plurality of memory cells, each of the memory cells having a first and a second source/drain areas, a control gate, and an insulating trap layer disposed between the control gate and a channel area lying between the first and the second source/drain areas. The trap layer includes a use bit area in proximity to the first source/drain area, for storing data depending on the presence or absence of electric charge to be trapped, and a non-use bit area in proximity to the second source/drain area, in which the electric charge is trapped while data is held in the use bit area. Preferably, in the state where erasing operation is completed, the non-use bit area is brought into a state where electric charge is trapped therein.

REFERENCES:
patent: 6331951 (2001-12-01), Bautista, et al.
patent: 6493261 (2002-12-01), Hamilton et al.

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