Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-18
2004-01-20
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185140
Reexamination Certificate
active
06680865
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor nonvolatile memory, and in particular, to a nonvolatile memory for which program operation is optimized by controlling its source potential.
BACKGROUND OF THE INVENTION
As one of the semiconductor nonvolatile memories, flash memory is available which uses a cell transistor having a floating gate. Since data can be retained in flash memory in the power-OFF state, and since its memory capacity is large and data can be read from it rapidly, flash memory is widely employed for portable phones and portable information terminals.
FIG. 1
is a diagram showing the general arrangement of flash memory. In
FIG. 1
, memory cells MC
1
, MC
2
and MC
3
, each constituted by a transistor having a floating gate FG, are arranged at intersections of word lines WL
1
, WL
2
and WL
3
and a bit line BL. For each cell transistor, an N-type source region S and an N-type drain region D are formed at the surface of a P-type substrate, and a floating gate FG and a control gate CG are formed, via an insulating film, over a channel region between the source and drain regions. The control gates CG are respectively connected to the word lines WL
1
, WL
2
and WL
3
, the drain regions D are connected to the bit line BL, and the source regions S are connected to source line SL.
Each cell transistor maintains a data “1” state, wherein no charges (e.g., electrons) are injected into the floating gate FG, and a data “0” state, wherein charges are injected. The threshold voltage is low for the data “1” and is high for the data “0” states. Therefore, when a middle voltage, one between the two threshold voltages, is applied to the word line WL and the source line SL is grounded, the reading of data from the memory cell is possible because a drain current difference exists between the two states. Further, when a multi-leveled memory cell is employed, the charges injected into the floating gate FG have at least three states, and these states are also detected through the drain current.
During the programming, for a cell transistor in a data “1” state (an erased state), wherein no charges are injected into the floating gate FG, the bit line BL is set at a high potential, such as 6 V, the word lineWL is set at a high potential, such as 10 V, and the source line SL is set to a low potential, such as a ground level. Thus, a hot electron is generated by the application of a high voltage between the source and the drain, and is injected into the floating gate FG. In this case, the ground potential is applied to a non-selected word line WL to prevent the cell transistor, which is not to be operated, from being rendered on.
During the erasing operation, the word line WL is set to a ground potential or a negative potential, the source line SL is set to a high potential, and the bit line is set in the floating state, so that charges on the floating gate FG are extracted toward the source region.
FIG. 2
is a circuit diagram showing a conventional source line voltage generator and a cell array. In a sector SCT, which includes a cell array, as in
FIG. 1
, cell transistors MC
1
, MC
2
and MC
3
are arranged at the intersections of word lines WL
1
, WL
2
and WL
3
and a bit line BL. The control gates of the individual cell transistors MC
1
to MC
3
are respectively connected to the word lines WL
1
, WL
2
and WL
3
, and the drain terminals are connected to the bit line BL. Further, the source terminals of the cell transistors MC of the sector SCT are connected to a common source line SL.
A program voltage generator
10
is connected to the bit line BL to generate the previously described high voltages during the programming. Further, a source line voltage generator
12
is connected to the source line SL.
During the programming, a high voltage of about 6 V is applied to the bit line BL, to which a selected cell transistor to be programmed (e.g., MC
3
in
FIG. 2
) is connected, and a high voltage of about 10 V is applied to the selected word line WL
3
. Also, 0 V is applied to the word lines WL
1
and WL
2
, which are not selected, so that non selected cell transistors (MC
1
and MC
2
in
FIG. 2
) are prevented from being rendered conductive.
However, even though the word lines WL
1
and WL
2
for the non selected cell transistors MC
1
and MC
2
is adjusted to 0 V, since a high voltage is applied to the bit line BL, the potential at the floating gate FG is raised due to the coupling with the drain region D connected to the bit line BL, and the cell transistors MC
2
and MC
2
may be rendered on. Accordingly, current leaks from these cell transistors are fed to the bit line BL, and due to a voltage drop resulting from a parasitic resistance RBL along the bit line BL, the drain potential of the selected cell transistor is lowered. Therefore, the source-drain voltage is not enough and a programming defect occurs.
In order to prevent this programming defect, conventionally, during the programming the source line voltage is adjusted so it is slightly higher than the ground potential. That is, during the programming, in accordance with a program control signal /PGM, which is set to level L, the source line voltage generator
12
in
FIG. 2
adjusts the potential on the source line SL to be slightly higher than ground potential Vss, and when the programming is not performed, the source line generator
12
adjusts the potential on the source line SL to be the ground potential Vss. Also during the programming, a transistor Q
1
is rendered off and a transistor Q
2
is rendered on upon the reception, via an inverter, of the program control signal /PGM. Further, the potential ARVss on the source line SL is adjusted by a resistor Rp so it is slightly higher than the ground potential Vss. Whereas when programming is not performed, the transistor Q
1
is rendered on and the potential ARVss on the source line SL is adjusted to be the ground potential Vss.
During the programming, the potential ARVss of the source line SL is set higher than the ground potential Vss, the source potential at the non-selected cell transistor is raised, and due to a back bias effect, the threshold voltage at that cell transistor is substantially raised, and a current leak at the non-selected cell transistor is prevented.
However, as the capacity of the non-volatile memory have been recently increased, the cell array region has been increased and the resistance RBL on the bit line BL and the resistance RSL on the source line SL becomes too high to be ignored. Further, when as in the memory cell MC
3
in
FIG. 3
the selected cell transistor is located away from both the program voltage generator
10
and the source line voltage generator
21
, the drain potential is lowered due to the resistance RBL on the bit line BL, the source potential is raised, and the drain-source voltage VDS at the cell transistor MC
3
is reduced. This unsatisfactory drain-source voltage causes the programming time to be extended and the programming disabled.
SUMMARY OF THE INVENTION
To resolve the above shortcoming, it is one objective of the present invention to provide a non-volatile memory for which programming is optimized.
To achieve this objective, according to one aspect of the present invention, in a non-volatile memory, the source potential of a selected cell transistor to be programmed is controlled to be changed in accordance with a distance between a program voltage generator connected to a bit line and to the selected cell transistor. In the preferred embodiment of the present invention, when the distance between the selected cell transistor and the program voltage generator is a first distance, the source potential at the selected cell transistor is controlled to be a first potential, and when the distance between them is a second distance longer than the first distance, the source potential at the selected cell transistor is controlled to be a second potential higher than the first potential. As a result, the drain-source voltage at the selected cell transistor to be programmed can be optimized, an
Arent Fox Kintner & Plotkin & Kahn, PLLC
Le Thong Q.
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