Nonvolatile memory device with NAND array

Details Nonvolatile memory device with NAND array Nonvolatile memory device with NAND array

1994-08-22

1996-06-04

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518517, 36518525, 36518522, G11C 700

Patent

active

055240941

ABSTRACT:
A semiconductor nonvolatile memory device which enables shortening of the time of the bit verification operation and thus high speed reading operations, including a first memory cell array connected to a first bit line, a second memory cell array connected to a second bit line, a first transistor operatively connecting the first bit line and a first node, a second transistor operatively connecting the second bit line and a second node, a precharging circuit for precharging the first and second bit lines, and an equalizing circuit for equalizing the sense amplifier, wherein, at the time of a verification read operation, the gate electrode of the transistor connected to the bit line on the reference side is given as input a control signal set to a level not more than a voltage comprised of the precharge voltage of that bit line plus the threshold voltage of that transistor.

REFERENCES:
patent: 5228106 (1993-07-01), Ang
patent: 5243573 (1993-09-01), Makihara
patent: 5297092 (1994-03-01), Johnson
patent: 5301160 (1994-04-01), McAdams

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