Nonvolatile memory device, in particular a flash-EEPROM

Details Nonvolatile memory device, in particular a flash-EEPROM Nonvolatile memory device, in particular a flash-EEPROM

2000-04-20

2002-02-26

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185130

Reexamination Certificate

active

06351413

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a nonvolatile memory device, in particular a flash-EEPROM.
BACKGROUND OF THE INVENTION
As known, memory arrays comprise a plurality of cells arranged on rows and columns, and each memory cell is identified by an own address, which, decoded, unambiguously addresses and biases the row and the column of the cell, so that the cell can be read and written. In general, the rows are known as word lines, and the columns are known as bit lines. In some cases a further subdivision in global lines and local lines is necessary; therefore local lines or columns connected directly to the cell to be addressed (to be read or written), are grouped in packets formed by a number of lines, usually a power of two, and are connected by respective selection circuits to a global line, addressed by a global decoder.
In general, standard decoding is an addressing system wherein the word or bit lines are of the same level to each other and are not organized hierarchically, and hierarchical decoding is an addressing system comprising global lines and local lines.
In flash memories, a further division into sectors is necessary (each sector being a block of cells having a common terminal and comprising an equal number of rows and columns), for which erasing is carried out. To avoid stress phenomena, detrimental to the cells, it is necessary to electrically isolate the various sectors to apply the high voltages (for example, voltages necessary for programming and erasing, and, for multi-level memories, also for reading), only to the selected sector. This division is dependent on the adopted erasing method, and two cases in particular can be distinguished:
erasing by the source terminal, with the gate terminal grounded: in this case the sectors are organized by columns, and the row is shared. This solution has the disadvantage that the cells not to be programmed, but connected to the row of the cell to be written, are subjected to gate stress during the programming; and
erasing by applying a negative voltage to the gate region; in this case, two different decoding types are possible, i.e., hierarchical column decoding, and hierarchical row decoding.
Two examples of hierarchical (vertical) column decoding are shown in
FIGS. 1 and 2
, wherein row decoding is standard and the column decoding is hierarchical.
In detail,
FIG. 1
shows a memory array
1
, comprising a plurality of sectors
2
, arranged on two columns separated from each other by two pairs of row decoders
3
, for the right- and left-hand sectors respectively. A respective column decoder
4
is arranged below each sector
2
. Each sector
2
comprises a plurality of memory cells
5
, shown partially only for one sector
2
.
In turn, the memory cells
5
are arranged on rows and columns; in particular the memory cells
5
arranged on a same row and belonging to a same sector
2
are connected to a same word line
6
, which extends along the entire width of each sector, from the respective row decoder
3
. In addition, the memory cells
5
arranged on a same column and belonging to a same sector
2
are connected to a same local bit line
8
, which extends along the entire height of each sector
2
, from the respective local column decoder
4
. Adjacent pairs of local bit lines
8
belonging to a same sector
2
are connected, through respective switches
10
, for example formed by pass transistors, to a same global bit line
11
; each global bit line extends along the entire respective sector column and is connected to pairs of local bit lines
8
belonging to vertically aligned sectors
2
. The global bit lines
11
are connected to a global column decoding circuit
12
, in turn connected to a reading stage
13
(comprising a plurality of sense amplifiers, not shown). The row decoders
3
, the local column decoders
4
, and the global column decoder
12
, receive respective address and control signals, and the bias voltages required at respective inputs, as shown in FIG.
1
.
The solution in
FIG. 1
can be used if the number of sectors is not too high, and does not alter excessively the shape of the array, here an elongate rectangle. In case of a large number of sectors, it is possible to use the solution of FIG.
2
.
FIG. 2
shows a memory array
1
′, comprising a plurality of sectors
2
, arranged on four columns and a plurality of rows. In particular, two row decoders
3
are arranged between each pair of sectors
2
. In memory array
1
′, it is necessary to double the number of reading circuits, as shown in the Figure by two reading stages
13
. As an alternative, it is possible to introduce an additional multiplexing level. Otherwise, the memory array
1
′ in
FIG. 2
is similar to those in FIG.
1
.
In the hierarchical column decoding just described, the length of the rows and columns cannot be long, thus limiting the number and dimensions of the sectors to be provided. In fact, a long column call cause leakage, whereas the length of the row affects the access time, due to the equivalent time constant RC of the word lines. However, the solutions designed to solve this problem are affected in turn by further problems. For example, to reduce the problem of the biasing delay in case of long word lines, it has been proposed to arrange, in parallel with each polysilicon word line, a metal line, connected at various points to the actual word line (metal strap technique). This solution makes it possible to reduce the resistance of the word lines, but reduces the reliability of the memory, since it increases the risk of short-circuiting between the metal lines, which must be arranged along the path of the row, i.e., along its width.
In addition, in case of hierarchical column decoding, the problem exists that the row decoders occupy a large area, and the memory array as a whole becomes voluminous.
In case of hierarchical row decoding, the situation is inverse, i.e., the column decoding is standard, and row decoding is hierarchical. An embodiment of a memory array with hierarchical row decoding is shown in FIG.
3
.
In detail,
FIG. 3
shows a memory array
1
″ comprising a plurality of sectors
2
, arranged on a plurality of rows and a plurality of columns, for example on four rows and eight columns, only some whereof are shown in FIG.
3
. Each sector row is associated to a global row decoder
15
, and each sector
2
is associated to a local row decoder
16
, which is divided into two parts, arranged respectively to the left and right of each sector
2
; in
FIG. 3
, the local row half-decoder
16
, arranged to the right of a sector
2
, forms a unit with the local row half-decoder
16
arranged to the left of the sector
2
adjacent on the right.
A plurality of global word lines
20
extends from each global row decoder
15
along the entire width of the memory array
1
″, i.e., along the entire row; each global word line
20
, formed by a metal line, is thus connected to a plurality of polysilicon local word lines
21
; in the example illustrated, for each sector
2
, two local word lines
21
are connected to a same global word line
20
, through a respective switch
22
, for example comprising a pass transistor.
Each row of sectors
2
is associated to a respective column decoder
23
, arranged alternately below and above the sector row; metal bit lines
24
extend from the column decoders
23
and are connected to the drain terminals of the memory cells
5
. Adjacent column decoders
23
have first common output lines
25
, connected to second output lines
26
and leading to a reading stage
27
.
Similarly to the above, the global row decoders
15
, the local row decoders
16
and the column decoders
23
receive respective address and control signals and the required bias voltages at the respective inputs, as shown in FIG.
3
.
The hierarchical row decoding shown in
FIG. 3
has disadvantages similar to those previously described for the hierarchical column decoding, i.e., the bit lines
24
, the length of which is determined by the height (number of rows) of

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