Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-09-19
2002-12-10
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185110
Reexamination Certificate
active
06493260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device. The invention is applicable to a flash memory, and may also be used in any type of memory; for example, it can advantageously be applied to a nonvolatile memory, such as an EPROM, EEPROM, and other types of memories.
2. Description of the Related Art
As is known, multilevel flash memories allow storing more than one bit inside each memory cell. Thereby, the capacity (storage density) of the memory is increased, the dimensions of the memory are reduced, and the storing cost per megabit is reduced.
Currently commercially available multilevel memories have dimensions of up to 256 Mbits (memories with NAND configuration), and up to 128 Mbits (memory with NOR configuration). The currently used multilevel memories have 2 bits per cell, allowing the threshold voltage of the cell to be modified within four separate distributions, as shown in FIG.
1
. Devices have been proposed, some of which are at the design stage, that can store 6 or more bits, corresponding to 64 or more separate distributions.
Despite the advantages associated with the greater data capacity, present multilevel flash memories have the problem that data reading is difficult. In particular, when the number of bits per cell is increased, the performances are correspondingly deteriorated, as regards to access time and reliability. In fact, the need to distinguish more distributions than bilevel devices, (which have only two storage slates) requires greater sensitivity of the reading system, which must be able to distinguish two currents differing for a few micro Amps, compared with the tens of micro Amps of bilevel cells. This results in a longer access time, irrespective of the adopted reading system, whether parallel or serial, of the current or threshold type.
FIG. 2
shows for example the current distribution as a function of gate-source voltage of memory cells programmed with two bits, read using a current system with a constant gate voltage (Vr), wherein the two bits stored in a cell to be read are detected by comparing the current supplied by the cell to be read, with three current references Irif
1
, Irif
2
, Irif
3
.
Consequently, reading a multilevel cell is intrinsically slower than reading a bilevel cell, specifically because of the greater accuracy required during reading. For example, the access time for a bilevel, 32 Mbit flash memory is less than 80 ns, whereas the access time for a multilevel memory with the same dimensions, with two bits per cell, is approximately 120 ns.
Consequently, the advantage due to the reduction of dimensions and costs of multilevel memories is obtained at the expense of speed and reliability. This situation is particularly disadvantageous in case of memories designed to store both information, for which a high speed and reliability is required, and information, for which a high capacity is more important. This is the case, for example, of memories storing both device operating codes, and data.
It should be noted that multilevel devices produced specifically for reducing storage costs per Mbit are advantageous only for large memory reductions; in fact, the additional circuitry necessary for accomplishing the greater accuracy required for carrying out memory reading and programming reduces the efficiency &eegr;
ar
of the device defined as:
η
ar
=
A
cel
A
dev
wherein A
cel
is the area occupied solely by the memory cells of the device, and A
dev
is the area occupied by the entire device.
With the present technologies, to obtain good efficiency, it is therefore necessary for the device to have dimensions of at least 64 Mbits. These devices are advantageous in particular for storing codes, which can be read sequentially and not randomly, for example by burst reading, which, at the expense of an initial delay known as latency, can subsequently reach reading speeds higher than 50 MHz. In this case, however, the data reading, which takes place randomly, is disadvantageous.
Another example of devices having conflicting requirements in different parts, are boot devices, which generally have a sector read directly when the system that includes the memory is switched on, such as for the BIOS of personal computers. In this case, it is important for the reading time to access the sector of the BIOS to be as short as possible, without however reducing the data storage capacity. The same applies to memory devices provided with an operative part such as a cache memory, for which a high reading speed is required, and with a part designed for storing large data or codes information.
SUMMARY OF THE INVENTION
According to principles of the present invention, a memory device allowing rapid, reliable reading of information stored in part of the memory, and yielding a high information storage density in another part of the memory is provided.
According to the present invention, a nonvolatile memory device is provided having a memory matrix with two portions, a first portion in which memory cells store M bits, and a second memory portion in which memory cells store N bits. The relative size of each portion can be established at manufacture or, preferably, a circuit is provided so that the relative size of each portion can be modified as selected by a user. For such a memory device, some of the memory access circuitry is common to both portions of the array, thus conserving space over having two separate memories. For example, the common portions may be the input and output pads. For increased savings in space, the common portions may also include one or more of the row decoder, the column decoder, the sense amplifier circuitry, the program and erase circuitry, and the input and output logic.
REFERENCES:
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5541886 (1996-07-01), Hasbun
patent: 5838610 (1998-11-01), Hashimoto
patent: 6044004 (2000-03-01), Kramer
patent: 0 766 254 (1997-04-01), None
patent: 0 788 113 (1997-08-01), None
patent: 0 961 287 (1999-12-01), None
Campardo Giovanni
Micheloni Rino
de Guzman Dennis M.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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