Static information storage and retrieval – Addressing – Sync/clocking
Patent
1994-04-18
1996-01-09
Nelms, David C.
Static information storage and retrieval
Addressing
Sync/clocking
365191, 365195, 36518523, 365226, G11C 800
Patent
active
054834961
ABSTRACT:
When execution of a program is interrupted during erasure or writing, electric charge normally remains due to high voltage. This charge is electrically discharged to thereby prevent erroneous erasure, erroneous writing, and erroneous reading. It comprises a timer circuit for producing a shortened program timing pulse when execution of a program is interrupted, together with a word line driver, a control line driver, and a bit line driver which are controlled by the timer circuit. A program-interrupting signal 30 is applied to a selector 23 which then switches the connected clock-generating circuit from a clock-generating circuit 21 to a clock-generating circuit 22 of a higher clock frequency in response to the signal 30. Therefore, when the execution of the program is interrupted, the shortened program timing pulse for interruption is applied to each memory cell. When execution of a program is interrupted during erasure or writing, erroneous erasure, erroneous writing, and erroneous reading can be prevented.
REFERENCES:
patent: 5265063 (1993-11-01), Kogure
patent: 5315557 (1994-05-01), Kim
patent: 5371715 (1994-12-01), Kim
patent: 5381366 (1995-01-01), Kawauchi
Mai Son
Nelms David C.
Seiko Instruments Inc.
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