Static information storage and retrieval – Floating gate – Multiple values
Patent
1997-07-09
1999-03-30
Nelms, David
Static information storage and retrieval
Floating gate
Multiple values
365184, G11C 1134
Patent
active
058896988
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a technique which is especially effective when applied to a multi-value data storing system in a semiconductor memory device and a nonvolatile semiconductor memory device, for example, to a technique which is effective when applied to a nonvolatile memory device (hereinafter referred to as the "flash memory") for batch-erasing a plurality of memory data electrically.
BACKGROUND ART
A flash memory uses nonvolatile memory elements each having a control gate and a floating gate similar to FAMOSs, as its memory cells, and each memory cell can be constructed of one transistor. In such a flash memory, for a programming operation, the drain voltage of the nonvolatile memory element is set to about 5 V, as shown in FIG. 12, and the word line connected to the control gate is set to about -10 V, so that the charge on the floating gate is drawn therefrom by tunnel current to set the threshold voltage to a low value (logic "0").
For the erasing operation, as shown in FIG. 13, the P-type semiconductor region p-well is set to about -5 V, and the word line is set to about 10 V, so that tunnel current is caused to flow to inject negative charges into the floating gate, thereby to set the threshold value to a high state (logic "1"). Thus, one memory cell is able to store the data of one bit.
Incidentally, there has been the concept of a so-called "multi-value" memory has been proposed in which data of two or more bits are stored in one memory cell so as to increase the storage capacity. An invention relating to such a multi-value memory is disclosed in Japanese Patent Laid-Open No. 121696/1984.
In a flash memory of the prior art, it is known that the variation of the threshold value is increased due to both a weak program (the disturb) or the like caused by the programming, reading and erasing operations of an adjacent bit and natural leakage (the retention), and consequently the half-value width (the width of the peak of the bell-shaped variation distribution at the position of a half peak value, as shown in FIG. 3) of the variation distribution of the threshold value corresponding to logic "0" and "1"increases with the lapse of time. The inventors have found that, with the lower level of the power supply voltage of future LSIs, the threshold voltage of the memory cells may exceed the marginal range for the read voltage by the broadening of the variation distribution with time, thereby to cause a malfunction.
This problem is especially serious in a multi-value memory for storing one memory element with data of a plurality of bits by the difference between the threshold values, because this difference is small for the individual data. In a flash memory, moreover, there is a technical problem for minimizing the processing time and the circuit scale intrinsic to the multi-value memory, because of the erasing and program verifying operations intrinsic to the nonvolatile memory device.
An object of the present invention is to provide a multi-value type nonvolatile memory device which can realize programming, reading and erasing operations of high accuracy performed in a short time while minimizing the increase in the circuit scale.
Another object of the present invention is to provide a method of sharpening the shape of the variation distribution of the threshold values, and accordingly, to a nonvolatile memory device capable of stably operating at a low voltage.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representative features of the invention to be disclosed herein will be briefly summarized in the following. transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is appl
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Kotani Hiroaki
Miwa Hitoshi
Hitachi , Ltd.
Nelms David
Tran M.
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