Nonvolatile memory device and reading method thereof

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185120

Reexamination Certificate

active

07872915

ABSTRACT:
A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of word lines, a plurality of cell blocks each including a plurality of cell strings, each of the cell strings including first and second select transistors and a plurality of memory cells, a plurality of sub bit lines commonly connected to the respective cell strings in same group, the cell blocks being grouped into a plurality of groups whose number is identical to or smaller than the number of the cell blocks, a plurality of group selectors configured to selectively connect the main bit lines to the sub bit lines of a selected group, and a plurality of page buffers configured to sense data of the memory cells through the main bit lines.

REFERENCES:
patent: 5969990 (1999-10-01), Arase
patent: 6678191 (2004-01-01), Lee et al.
patent: 1998-061435 (1998-10-01), None
patent: 1998-066563 (1998-10-01), None
patent: 10-2005-0081391 (2005-08-01), None
patent: 10-2005-0092199 (2005-09-01), None
Notice of Allowance for Korean Application No. 10-2007-0111199.

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