Nonvolatile memory device and data write method for...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185140, C365S185130, C365S185230

Reexamination Certificate

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11176324

ABSTRACT:
A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) being arranged in a column direction, and each of the memory cell blocks including M memory cells (M is an integer equal to or greater than 2), a plurality of wordlines, a plurality of first control gate lines, a plurality of first control gate switches, a plurality of second control gate lines, and a plurality of bitlines.

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Yatsuda, et al. Hi-MNOS II technoogy for a 64-kbit byte-eraseable 5-V-only EEPROM. Feb. 1985, IEEE Transactions of Electron Devices, vol. 32, Issue 2, 224-231.

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