Nonvolatile memory cell for eeprom including a floating gate to

Details Nonvolatile memory cell for eeprom including a floating gate to Nonvolatile memory cell for eeprom including a floating gate to

1988-02-02

1990-01-16

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 357 235, G11C 1140, H01L 2979

Patent

active

048948020

ABSTRACT:
Disclosed is a nonvolatile memory cell which utilizes a tunnel window to discharge the floating gate at a location spacially displaced from the program path for the cell. Also disclosed is a process for making such a memory cell.

REFERENCES:
patent: 4668970 (1987-05-01), Yatsuda et al.
patent: 4672409 (1987-06-01), Takei et al.
patent: 4688078 (1987-08-01), Hseih
Samachisa, Gheorghe et al., "A 128K Flash EEPROM Using Double-Polysilicon Technology," IEEE Journal of Solid-State Circuits, vol. SC022, No. 5, Oct. 1987.
H. Kume et al., "A Flash-Erase EPPROM Cell With an Asymmetric Source and Drain Structure", IEEE Technical digest of IEDM 1987, pp. 560-563.
Satyen Mukherjee et al., "A Single Transistor EEPROM Cell and Its Implementation in a 512K CMOS EEPROM" IEEE Technical Digest of IEDM 1985, pp. 616-619.

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