Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-04-22
2002-12-31
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030, C365S185010, C257S316000, C257S317000
Reexamination Certificate
active
06501680
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the benefit of Application No. P1999-43252, filed in Korea on Oct. 7, 1999, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor memory, and more particularly, to nonvolatile memory, in which a flash memory cell having two floating gates is provided for storing a significant amount of information per cell, and a method for sensing data therefrom.
2. Background of the Related Art
In general, there is a volatile memory which permits erasing stored information and saving new information and a nonvolatile memory which permits storing information only once. In the volatile memory, there are RAM data which are writable thereto and readable therefrom, and in the nonvolatile memory, there are ROM (Read Only Memory), EPROM (Erasable Programmable ROM), and EEPROM (Electrically Erasable Programmable ROM) data. The ROM cannot be programmed again once information is stored, but the EPROM and EEPROM an be programmed again once infonnation stored therein is erased. The EPROM and EEPROM have the same information programming operation, but different information erasing operation. The EPROM erases information stored therein using a U.V. ray, while the EEPROM erases information stored therein using electricity. Keeping pace with demands for a large-sized memory according to the development of the information industry, DRAM is the most widely used as a mass storage media. However, DRAM requires a storage capacitor above a certain size which requires periodic refreshment. Accordingly, instead of DRAM, there have been extensive studies on EEPROM which requires no refreshment. However, since EEPROM also permits writing either ‘1’ or ‘0’ thereon, a device packing density corresponds to a number of memory cells. Therefore, when it is intended to use EEPROM as data storage media, the greatest problem is that the cost per bit is too high. In order to solve this problem, there is active research on a multi-bit memory cell. The multi-bit memory cell permits significantly increased data storage density in the same area of a chip without reducing memory cell size by storing two or more than two data in one memory cell. The multi-bit memory cell is programmed in multiple stages of threshold voltage levels. That is, in order to program two bits of data in one cell, each of the cells should be programmed in four stages of threshold voltage levels as is known from 2
2
=4. In this instance, the threshold levels in each cell correspond to logic states of 00, 01, 10, and 11. Accordingly, in order to increase a number of bits per cell by programming the cell in more levels, dispersion of each of the threshold voltage levels should be reduced by adjusting the threshold voltage levels precisely.
A related art nonvolatile memory, cell array thereof, and method for sensing data therefrom will be explained with reference to the appended drawings.
FIGS. 1A and 1B
illustrate unit cells of related art nonvolatile memory cells.
FIG. 2
illustrates a cell array of related art nonvolatile memories.
FIG. 3A
illustrates cell states at threshold voltages according to the first related art method, and
FIG. 3B
illustrates cell states at control gate voltages and reference currents according to the first related art method.
The related art nonvolatile memory is flash memory, and a unit cell is provided with, as shown in
FIGS. 1A and 1B
, a stack of a first gate insulating film
2
, a floating gate
3
, a second insulating film
4
, and a control gate
5
on a first conduction type semiconductor substrate
1
, and second conduction type drain
6
a
and source
6
b
in the semiconductor substrate
1
on opposing sides of the floating gate
3
. A channel region is formed in the semiconductor substrate
1
under the floating gate
3
when a write or read operation is performed.
Referring to
FIG. 2
, a cell array of related art nonvolatile memories is provided with a plurality of flash memory cells, wordlines
10
, bitlines
11
, sourcelines
12
, and a common sourceline
13
. There is a matrix of the plurality of flash memory cells each having a floating gate and a control gate, with the plurality of wordlines
10
formed in an axial direction for providing a voltage to control gates in the flash memory cells in a longitudinal direction. There is a drain contact DS for every two unit cells, and there are a plurality of the bitlines
11
disposed in a longitudinal direction, each connecting the drain contacts DS in the axial direction. And, there are a plurality of the sourcelines
12
disposed in the axial direction each connecting sources
6
b
of the unit cells in the longitudinal direction, and there is the common sourceline
13
disposed the axial direction.
TABLE 1
bitline
wordline
common sourceline
Programming
5~6 V
10~12 V
0 V
Read
1 V
5~10 V
0 V
Erase
float
−10 V or 0 V
12 V or 3.3~5 V
Write, read, and erase operations of the flash memory
14
selected from the related art nonvolatile memory having the aforementioned system will be explained with reference to
FIGS. 1A and 2
, and TABLE 1.
Referring to
FIGS. 1A and 2
, in the write operation, after selecting one of the flash memory cells at a crossing point of a selected wordline
10
and a selected bitline
11
, a voltage of 5~6V is provided to a drain
6
a
of the selected flash memory cell, a voltage of 10~12V is provided to the wordline
10
, and a voltage of 0V is provided to the common sourceline
13
causing current to flow in the channel, that, in turn, causes hot electrons to migrate from the channel to the floating gate
3
through the first gate insulating film
2
. Upon reception of the electrons to the floating gate
3
, the flash memory cell is involved in a pull up of the threshold voltage, stopping the write operation when the threshold voltage reaches a desired threshold voltage.
Referring to
FIGS. 1A and 2
, in the read operation, after a voltage of 5~10V is provided to the wordline
10
, a voltage of approximately 1V is provided to the bitline
11
, and a voltage of 0V is provided to the common sourceline
13
, current flowing through the channel is sensed, and a threshold voltage corresponding to the current is read to read stored information.
Referring to
FIGS. 1A and 2
, in the erasure operation, the bitline
11
is floated, a voltage of −10V or 0V is provided to the wordline
10
, a voltage of 12V or 3.3~5V is provided to the common sourceline
13
, causing electron tunneling of electrons stored in the floating gate
3
to the source
6
b
through the first gate insulating film
2
. In this instance, a plurality of the flash memory cells connected with the common sourceline
13
can be erased at the same time, block by block. Levels of the threshold voltages in the flash memory cell can be adjusted to provide states of 2, 4, 8, or over. A cell with equal to or more than four states is called as a multilevel cell.
TABLE 2
0 state
cell current > reference current
1 state
cell current > reference current
TABLE 3
00 state
first reference current > cell current
01 state
second reference current > cell current > first reference current
10 state
third reference current > cell current > second reference current
11 state
cell current > third reference current
Next, methods for sensing cells having one bit information which have two states, and cells having two bit information, which have four states, will be explained with reference to
FIGS. 3A
,
3
B, TABLE 2,
FIGS. 4A
,
4
B, and TABLE 3.
When one bit information is stored, a case where a cell current is higher than a reference current is defined as ‘0 state’ and a case where the cell current is lower than the reference current is defined as ‘1 state’, as illustrated in FIG.
3
A and TABLE 2. The cell and reference currents are a result of measuring I-V characteristics of a flash memory cell where one reference threshold voltage is set. Since writing to many flash memory cells is conducted, the states show a state as shown in
FIG. 3B
Auduong Gene N.
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
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