Nonvolatile memory cell array architecture for high speed...

Details Nonvolatile memory cell array architecture for high speed... Nonvolatile memory cell array architecture for high speed...

2011-01-04

2011-01-04

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185260, C365S185230

Reexamination Certificate

active

07864576

ABSTRACT:
When different word lines are accessed sequentially, to perform access operations in parallel, a word decoder overlaps a part of activation periods of those word lines. That is, a nonvolatile semiconductor memory is capable of pipeline processing for performing access operations in parallel. All the combinations of bit lines and source lines that are connected to the drains and the sources of nonvolatile memory cells are different from each other. Therefore, even when plural word lines are activated to perform plural read operations in parallel, a memory cell current is allowed to flow only between the drain and the source of a nonvolatile memory cell concerned. As a result, random access in which desired nonvolatile memory cells are accessed sequentially is enabled in a nonvolatile semiconductor memory having a pipeline function for performing plural read operations in parallel.

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