Nonvolatile memory cell arrangement

Details Nonvolatile memory cell arrangement Nonvolatile memory cell arrangement

2005-11-18

2008-08-12

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S063000, C257S211000, C257S381000, C257S758000

Reexamination Certificate

active

07411822

ABSTRACT:
Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.

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