Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Low workfunction layer for electron emission
Reexamination Certificate
2002-01-02
2003-09-09
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Low workfunction layer for electron emission
C257S316000
Reexamination Certificate
active
06617605
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a nonvolatile memory cell and to a method for producing the memory cell. A nonvolatile memory is typically an EPROM (electrically programmable read only memory) or an EPROM-like memory, such as an EAROM (electrically alterable ROM), an EEPROM (electrical erasable PROM), a Flash-EPROM or an OTPROM (one-time programmable ROM). Tunnel contacts, also called tunnel junctions, are used in a large number of semiconductor components, such as tunnel diodes and nonvolatile memories. Tunnel contacts are electrical connections between two electrodes that, in the classical sense, must be considered as being insulated from each other. If the two electrodes are spaced apart by a small distance of only a few nanometers, then quantum mechanisms explain the current flow between the electrodes when a voltage is applied. In this case, the electrons do not overcome the potential barrier that is arranged between the electrodes as a result of applying an appropriately high voltage to lift the electrons into the conduction band of the potential barrier. In this case, significantly lower voltages establish a current flow between the electrodes. This current flow is called the tunnel current and tunnels through the insulating barrier between the electrodes.
Current rewriteable, permanent semiconductor memories are based on an MOS transistor (metal oxide semiconductor) that has an additional electrically insulating storage electrode (floating gate) located between its channel and its gate electrode. Typically, the storage electrode is completely insulated by a thin oxide layer and is charged and discharged by a tunnel current that is produced by Fowler-Nordheim tunneling or by high-energy electrons (hot electrons). During the charging and discharging of the storage electrodes, electrons tunnel through the thin oxide layer. As a result of the high-energy tunnel electrons, faults, such as broken bonds, occur in the thin oxide layer. These faults can form a conductive path between the storage electrode and the channel, or between the storage electrode and the source region. The charge flows away from the storage electrode via such a conductive path, even if no voltage is present on the gate, source or drain, and the storage cell loses the information stored in it. As a result of the produced conductive path, the lifetime of the memory is presently limited to about 10
6
writing and erasing processes. Nonvolatile memory cells of this type are described, for example, in U.S. Pat. No. 5,844,842 and in U.S. Pat. No. 5,870,337. The degradation of the insulating film that insulates the floating gate electrode, and therefore the formation of a conductive path, is also described there.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an EEPROM-like memory and a method for producing the memory which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a nonvolatile memory cell in which a parasitic, possibly permanent conductive current path is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, an EPROM-like memory that includes a substrate having a source region, a drain region, and a channel. The memory includes a gate stack formed by a gate oxide, a storage electrode, a second gate oxide and a gate electrode. The gate oxide is configured on the substrate above the channel. The storage electrode is configured on the gate oxide. The second gate oxide is configured on the storage electrode. The gate electrode is configured on the second gate oxide. The memory includes an interspace that is configured between the drain region and the storage electrode. The interspace contains either a gas or a vacuum. The memory includes an outer spacing web that is configured laterally beside the gate stack. The outer spacing web is also configured on the drain region. The outer spacing web is made of doped polycrystalline silicon.
The tunnel barrier that is used in the present invention consists of gas or is a vacuum. As opposed to silicon oxide, which is normally used as the tunnel barrier in rewriteable, permanent semiconductor memories, the tunnel barrier that consists of gas or that is a vacuum is degradation-free. The tunnel contact includes a first electrode
1
, a second electrode
2
, and an interspace
3
that is located between the first electrode
1
and the second electrode
2
. The interspace
3
is filled with gas or is evacuated.
The distance between the first electrode
1
and the second electrode
2
is such that a tunnel current can flow between the two electrodes.
Since the interspace
3
is filled with gas or is evacuated, it is sealed off all around. The surface of this termination and therefore the surface of the interspace
3
is formed both by the first electrode
1
and by the second electrode
2
. Since the two electrodes are insulated from each other, part of the surface of the interspace
3
consists of an insulating material. If a current flows from the first electrode
1
to the second electrode
2
, then the current is divided into two partial currents. The first partial current represents a tunnel current through the interspace
3
and the second partial current represents a current along the surface of the insulating material which forms part of the surface of the interspace
3
. Therefore, the current that flows between the first electrode
1
and the second electrode
2
at least partially tunnels through the interspace
3
that is filled with gas or that is evacuated.
In another embodiment, any current that flows between the first electrode
1
and the second electrode
2
tunnels through the interspace
3
that is filled with gas or that is evacuated. This ensures that the electrical connection between the two electrodes is produced exclusively via the interspace
3
. Even if a further dielectric layer, which is not free of degradation by tunnel currents, is arranged between the first electrode
1
and the second electrode
2
, in series with the interspace
3
, then this is inconsequential for the functioning of the tunnel contact, since the interspace
3
continues to separate the two electrodes from each other as a degradation-free barrier.
Advantageously, the tunnel contact is integrated into a rewriteable, permanent semiconductor memory. As a result, the lifetime of the semiconductor memory is advantageously substantially lengthened and far more writing and erasing processes than the currently usual 10
6
are possible.
Preferably, the storage electrode
11
of a memory cell
10
is charged or discharged via the tunnel contact. As a result, the advantageous properties of the tunnel contact are integrated into the existing structures for producing nonvolatile semiconductor memories.
In an advantageous embodiment of the invention, the memory
10
is an EPROM-like memory, such as an EAROM, EEPROM, EPROM, Flash-EPROM or an OTPROM.
A first additional tunnel layer
4
is arranged between the first electrode
1
and the interspace
3
and/or a second additional tunnel layer
5
is arranged between the second electrode
2
and the interspace
3
. The additional tunnel layers
4
and
5
are protective layers for the electrodes
1
and
2
, which can consist of for example, an oxide layer. The first additional tunnel layer
4
, or respectively, the second additional tunnel layer
5
do not reduce the advantageous properties of the degradation-free tunnel contact, since even if the first additional tunnel layer
4
or the second additional tunnel layer
5
become conductive as a result of degradation effects, the interspace
3
continues to be present as a degradation-free tunnel barrier that insulates the first electrode
1
from the second electrode
2
.
In another embodiment, the first electrode
1
has a first region
6
and/or the second electrode
2
has a second region
7
. The first region
6
, or respectively, the second r
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nelms David
Nguyen Thinh
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