Nonvolatile memory cell and data latch incorporating...

Details Nonvolatile memory cell and data latch incorporating... Nonvolatile memory cell and data latch incorporating...

2011-08-30

2011-08-30

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S189050

Reexamination Certificate

active

08009483

ABSTRACT:
A nonvolatile memory cell includes: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.

REFERENCES:
patent: 5465231 (1995-11-01), Ohsaki
patent: 5666308 (1997-09-01), Ota
patent: 7558111 (2009-07-01), Eftimie et al.
patent: 7630247 (2009-12-01), Noda
patent: 7751256 (2010-07-01), Chan et al.

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