Nonvolatile memory cell

Details Nonvolatile memory cell Nonvolatile memory cell

1991-05-16

1992-07-14

Wojciechowicz, Edward J.

357 13, 357 55, H01L 2968

Patent

active

051307693

ABSTRACT:
A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.

REFERENCES:
patent: 4561004 (1985-12-01), Kuo et al.
patent: 4765473 (1988-08-01), Kuo
patent: 4957877 (1990-09-01), Tam et al.
patent: 4958321 (1990-09-01), Chang
patent: 4967398 (1990-10-01), Yokoyama et al.
A. Scheibe and Heinz Schulte, "Technology of a New N-Channel One-Transistor Earom Cell Called Simos" May 5, 1977.
Duane H. Oto et al., "High-Voltage Regulation and Process Considerations for High-Density 5V-Only E.sup.2 PROM's" Oct. 5, 1983.

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